Internal Voltage Generation Circuit With Timed Voltage Stabilization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional semiconductor apparatuses face performance degradation due to the continuous operation of capacitors in voltage stabilization, which degrades circuit performance as they are connected to the output node all the time, leading to inefficient charging and discharging processes.

Innovation Solution

An internal voltage generation circuit with an active driver, a standby driver, and a voltage stabilizer that starts and stops voltage stabilization operations based on an active enable signal, limiting the capacitor's operation time by disconnecting it after a predetermined time to allow the active driver to take over voltage supply.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the capacitor is connected to the output node all the time to stabilize voltage, then voltage stabilization ability is improved, but circuit performance degrades due to continuous charging and discharging operations

Engineering Contradiction:
Improvevoltage stabilization abilityVSAvoidcircuit performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies the dynamics principle by making the capacitor connection dynamic rather than static. The capacitor is connected to the output node only during specific periods (when active enable signal is disabled or during predetermined time after enabling) and disconnected at other times. This dynamic connection controlled by timing circuits allows the system to adapt between voltage stabilization needs and circuit performance requirements, resolving the contradiction between continuous stabilization and performance degradation.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the capacitor has large capacity to improve voltage stabilization, then voltage stabilization ability is improved, but charging process degrades circuit performance

Engineering Contradiction:
Improvevoltage stabilization abilityVSAvoidcharging time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-charging the capacitor during periods when the active driver is not operational (when active enable signal is disabled). The capacitor is charged in advance before the active driver needs to take over, so that when the active driver becomes active, the capacitor is already charged and ready to provide immediate voltage stabilization without delaying the charging process and degrading circuit performance.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution improves circuit performance by reducing the operational time of the capacitor, ensuring efficient voltage stabilization and maintaining stable voltage levels, thereby enhancing the semiconductor apparatus's overall performance.

Implementation Method 1

a capacitor C1 configured to stabilize the internal voltage Vint

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20140347093A1Semiconductor apparatus
Publication Date: 2014.11.27 SK HYNIX INC
  • US20140347093A1 patent drawing
  • US20140347093A1 patent drawing
  • US20140347093A1 patent drawing

AI summary

An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after the active enable signal is enabled.