Interpolated Delay Line Circuit for Higher TDC Resolution
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Solution Overview
Problem
Time to digital converters face limitations in resolution due to minimum stage delay constraints in inverter circuits, which restrict the precision of converting time-based signals into digital values.
Innovation Solution
The implementation of a time delay circuit with dual delay lines and interpolation circuits, where signals are propagated through multiple delay circuits with feedback, allowing for enhanced resolution by generating intermediate signals through analogue interpolation, thereby increasing the precision of time difference measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If inverter circuits are used for time delay, then the circuit structure is simple, but the resolution is limited due to minimum stage delay constraints
Solution Approach 1:
The delay line is segmented into multiple stages with delay elements and interpolation circuits. Each stage contributes to the overall delay while interpolation circuits between stages generate intermediate signals that increase resolution without requiring proportionally higher circuit complexity
Solution Approach 2:
Interpolation circuits are introduced as intermediary elements between delay stages. These circuits generate intermediate signals that provide additional timing information, effectively increasing measurement precision without requiring the delay elements themselves to be more complex
2Measurement precision
If multiple delay circuits are used to increase resolution, then measurement precision improves, but device complexity increases
Solution Approach 1:
The delay line is divided into multiple manageable stages, each with controlled complexity. This segmentation allows resolution to be increased by adding stages while keeping each individual stage relatively simple and modular
Solution Approach 2:
Interpolation circuits generate intermediate signals that provide more timing information than the basic delay stages alone. This partial action approach increases resolution by adding only the necessary intermediate elements rather than completely redesigning the entire delay structure
Data Source
AI summary
A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.