Interpolated Sampling Ground-Penetrating Radar for Noise Efficiency
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Solution Overview
Problem
Traditional ground-penetrating radar (GPR) systems face challenges in achieving high-resolution measurements at low cost and low power consumption due to sub-optimal noise efficiency and high noise levels, particularly when operating at high speeds.
Innovation Solution
The implementation of high-speed interpolated sampling using a GPR transmitter/receiver configured to obtain time-offset linearly sampled sequences, constructing a composite measurement waveform from interdigitated sequences with randomized or pseudo-randomized sampling orders, and applying discrete time filters to enhance signal recovery and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sub-sampling scheme is used to achieve high resolution measurements at low cost, then measurement resolution is improved, but noise efficiency deteriorates and noise levels increase
Solution Approach 1:
The sampling process is segmented into multiple interleaved sub-ADCs that each sample at lower rates, with samples from different sub-ADCs combined to achieve high effective sampling rate. This segmentation allows the system to achieve high resolution measurements while distributing the sampling burden across multiple lower-speed channels, improving noise efficiency.
Solution Approach 2:
The patent transitions from single-dimensional sequential sampling to multi-dimensional parallel sampling by introducing multiple interleaved sub-ADCs operating simultaneously. This dimensional expansion in the sampling architecture enables the system to achieve high effective sampling rates without requiring a single high-speed ADC, thereby improving noise efficiency while maintaining measurement resolution.
2Reliability
If high speed sampling is implemented to improve signal detection, then signal energy recovery is improved, but power consumption and cost increase
Solution Approach 1:
The high-speed sampling function is segmented across multiple lower-speed sub-ADCs that operate in parallel. Each sub-ADC consumes less power individually, but their combined operation achieves the effective high sampling rate needed for improved signal detection. This segmentation resolves the contradiction between signal detection capability and power consumption.
Solution Approach 2:
Instead of using a single high-speed ADC that would consume high power, the patent creates multiple copies of lower-speed ADCs that are interleaved. These copied ADC channels work together to achieve the same effective sampling rate as a single high-speed ADC, but with reduced power consumption and lower cost.
3Use of energy by moving object
If equivalent time sampling is used to reduce power consumption, then power efficiency is improved, but measurement noise increases
Solution Approach 1:
The equivalent time sampling approach is segmented into multiple interleaved sub-ADCs that each operate at lower speeds. By distributing the sampling across multiple channels and combining their outputs, the system maintains power efficiency while reducing measurement noise through the combined signal energy from all sub-ADCs.
Solution Approach 2:
Samples from multiple interleaved sub-ADCs are merged and combined to form the final measurement signal. This merging process accumulates signal energy from all channels while averaging out random noise, thereby improving signal-to-noise ratio while maintaining the power efficiency of equivalent time sampling.
Data Source
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AI summary
Embodiments of the disclosed technology use high-speed interpolated (interdigitated) sampling for the specific purpose of GPR (Ground-Penetrating RADAR). This technology solves several issues associated with high-speed sampling in GPR which included 1) dynamic range limitations, 2) regulatory compliance issues, 3) sampler core offset error, and 4) timing errors. High-speed interpolated sampling GPR is implemented using a high-speed ADC in combination with trigger logic (such as an FPGA) and a programmable delay generator. The FPGA or other trigger logic generates a series of randomly dithered trigger pulses. A variable delay generator (or "Vernier") is synchronously controlled in order to produce the fractional timing. The timing of the pulses is randomly or pseudo-randomly dithered, and the phase of the interpolation is shuffled in order to avoid producing discrete spectral lines in the radiated RADAR signal.