Interpolated Time Stamp Synchronization Beyond Clock-Speed Limits
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Solution Overview
Problem
Conventional time stamp circuits face limitations in achieving high resolution due to the need for high-speed clocks, making it difficult to generate precise time stamps for high-speed events, as the resolution required exceeds the capabilities of traditional electronic time stamp circuits.
Innovation Solution
The development of a time stamp apparatus with a flash-based architecture that interpolates between clock edges to improve resolution, combining a coarse time stamp with a fine time stamp generated by a synchronizer and an interpolator, allowing for higher precision without the need for high-speed clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional electronic time stamp circuits use a digital counter that increments at each rising edge of an oscillating clock signal, then the circuit structure is simple and easy to manufacture, but the measurement precision is limited by the clock speed and cannot achieve high resolution for high-speed events
Solution Approach 1:
The patent divides the time measurement into two segments: a coarse time stamp generated by a digital counter that increments at each rising edge of the clock signal, and a fine time stamp generated by an interpolator that measures the time between clock edges. This segmentation allows the system to achieve high resolution without requiring the entire circuit to operate at ultra-high speeds, thus resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent introduces a synchronizer as an intermediary component that coordinates the coarse time stamp generator and the fine time stamp generator. The synchronizer ensures that both generators are synchronized to the same clock signal and that their outputs can be properly combined. This intermediary mechanism enables the integration of simple counter-based measurement with complex interpolation-based measurement, achieving high resolution while maintaining manageable circuit complexity
2Measurement precision
If the clock speed is increased to achieve higher time stamp resolution, then the measurement precision improves, but the device complexity and difficulty of generating high-speed clocks increase significantly
Solution Approach 1:
The patent employs a dynamic interpolation technique where the fine time stamp generator dynamically calculates the fractional time between clock edges based on the actual timing of the event signal. This dynamic approach allows the system to achieve variable resolution without requiring a fixed high-speed clock, making the system easier to manufacture while maintaining high measurement precision
Solution Approach 2:
The patent transitions from a single-dimension time measurement (single clock frequency) to a two-dimension measurement approach by combining coarse time stamps (integer clock cycles) with fine time stamps (fractional clock cycles). This dimensional change allows the system to achieve high resolution without proportionally increasing clock speed, thereby improving ease of manufacture while maintaining measurement precision
3Productivity
If a flash-based architecture with interpolator is used to achieve high resolution time stamping, then the measurement precision and data throughput increase, but the device complexity increases
Solution Approach 1:
The patent implements preliminary action by having the coarse time stamp generator continuously count clock cycles and prepare coarse time stamp values before they are needed. The synchronizer also continuously monitors and maintains synchronization between the coarse and fine generators. This preliminary preparation allows the system to handle multiple events in parallel with high data throughput while managing circuit complexity through pre-computed values and continuous synchronization
Data Source
AI summary
Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally limited by clock speed. Here, an apparatus is provided that performs time stamp operations and is not generally limited by clock speed. This apparatus generally uses an interpolator, counter, lathing circuits, and a synchronizer. Typically, the interpolator provides a residue signal to the synchronizer, and the synchronizer can determines whether to add the interpolation signal to a counter state based at least in part on a comparison of an event signal and the residue signal.