Interpolating Delay Chain for Fine-Step Digital Clock Synthesis
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Solution Overview
Problem
Conventional digital clock synthesis units produce significant jitter and phase noise due to large delay steps and limited frequency granularity, making them unsuitable for many applications.
Innovation Solution
A programmable delay element and variable-length delay chain that perform phase interpolation using an interpolating multiplexer, allowing for fractional unit delay steps and fine adjustments in frequency and phase, enabling the generation of I/Q signals in end-tap or center-tap configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital clock synthesis units use discrete frequency steps, then the DCO can assume only a finite number of oscillation frequencies, but this results in large delay steps and significant jitter and phase noise
Solution Approach 1:
The delay chain is divided into multiple individual delay elements, each contributing a portion of the total delay. This segmentation allows the overall delay to be adjusted in finer steps by individually controlling each delay element, thereby reducing the granularity of frequency steps and minimizing jitter and phase noise in the synthesized clock signal.
Solution Approach 2:
The delay elements are made dynamically controllable through digital control signals that can adjust the delay amount of each element. This dynamic control enables continuous adjustment of the total delay chain delay, allowing the DCO to achieve fine frequency steps and reduce quantization noise analogous to jitter and phase noise.
2Device complexity
If a DCO uses coarser frequency steps to simplify design, then device complexity is reduced, but the peak phase error and jitter increase
Solution Approach 1:
The delay chain is divided into multiple individual delay elements, each contributing a portion of the total delay. This segmentation allows the overall delay to be adjusted in finer steps by individually controlling each delay element, thereby reducing the granularity of frequency steps and minimizing jitter and phase noise in the synthesized clock signal.
Solution Approach 2:
An interpolating delay element is introduced as an intermediary component between the digital control signal and the delay chain. This interpolator uses the least significant bits of the control signal to perform phase interpolation, enabling fine frequency adjustments without requiring a complete redesign of the entire DCO structure, thus balancing complexity and accuracy.
3Measurement precision
If the delay chain uses more delay elements to achieve finer frequency steps, then frequency granularity is improved, but the device complexity and area increase
Solution Approach 1:
Each delay element in the chain is designed to be multi-functional, capable of providing different delay amounts based on digital control signals. This universality allows a smaller number of delay elements to achieve fine frequency steps compared to a traditional design where each element provides a fixed delay amount, thereby reducing the overall area required for the delay chain.
Solution Approach 2:
The delay elements are made dynamically controllable through digital control signals that can adjust the delay amount of each element. This dynamic control enables continuous adjustment of the total delay chain delay, allowing the DCO to achieve fine frequency steps and reduce quantization noise analogous to jitter and phase noise.
Data Source
AI summary
A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.