Interpolating Delay Chain for Low-Jitter Digital Clock Synthesis
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Solution Overview
Problem
Conventional digital clock synthesis units produce significant jitter and phase noise due to large delay steps and frequency granularity, making them unsuitable for many applications.
Innovation Solution
A programmable delay element and variable-length delay chain that perform phase interpolation using current-mode logic and thermometer-coded digital signals, allowing for fractional unit delay steps and scalable delay steps with identical delay elements, enabling the generation of I/Q signals in end-tap or center-tap configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional digital clock synthesis units use discrete frequency steps, then the DCO can assume a finite number of oscillation frequencies, but this creates jitter and phase noise on the synthesized clock
Solution Approach 1:
The patent changes the fundamental parameter of frequency control from discrete steps to continuous adjustment by introducing a delay chain with variable length. The delay chain allows the DCO to adjust its oscillation frequency continuously by varying the signal propagation delay, eliminating the quantization noise and jitter associated with discrete frequency steps while maintaining digital control capability
2Reliability
If a DCO with finer frequency steps is used, then less jitter is introduced on the output clock, but the device complexity increases
Solution Approach 1:
The patent segments the frequency control function into two independent parts: a coarse adjustment mechanism using discrete delay elements and a fine adjustment mechanism using an interpolating delay element. This segmentation allows achieving fine frequency steps without proportionally increasing overall device complexity, as each segment handles a specific range of adjustment
3Measurement precision
If the delay chain length is variable, then fine adjustments to frequency and phase are enabled, but the device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent introduces an interpolating delay element as an intermediary component between the discrete delay elements. This intermediary performs phase interpolation by combining signals from adjacent delay stages, enabling fine frequency and phase adjustments without requiring a completely new control mechanism. The interpolating element acts as a mediator that translates coarse discrete delays into fine continuous adjustments
Data Source
AI summary
A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Optionally, the programmable delay element utilizes current-mode logic (CML) and the control signal is a thermometer coded digital signal. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.