Interpolating TDC Flip-Flops for Sub-Inverter Delay Resolution
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Solution Overview
Problem
Time-to-digital converters (TDCs) have limited resolution due to the delay of a unit cell in their delay line, which restricts their ability to accurately measure time intervals in high-speed applications.
Innovation Solution
The design incorporates a delay line for generating delayed versions of a signal and a sampling mechanism that samples the difference between these delayed signals, allowing for sub-unit delay resolution by using interpolating flip-flops that sample between consecutive delay units, effectively achieving timing resolution less than the unit delay of a single inverter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay line with unit cells is used to measure time intervals, then the TDC can generate delayed versions of signals, but the resolution is limited by the delay of a single unit cell
Solution Approach 1:
The delay line is segmented into multiple unit cells, each contributing a portion of the total delay. By dividing the delay path into discrete segments, the system can achieve fine-grained time measurement through combinatorial selection of segment delays, improving resolution without requiring a single complex delay element
Solution Approach 2:
The patent transitions from measuring time delays in a single dimension (serial delay units) to using multiple parallel delay paths with different delay characteristics. This dimensional expansion allows the system to achieve sub-unit delay resolution by combining measurements from multiple delay units operating in parallel
2Measurement precision
If the TDC uses conventional delay line design, then the structure is simple, but the timing resolution cannot exceed the unit cell delay
Solution Approach 1:
The system pre-generates multiple delayed versions of the input signal through the delay line before the comparison stage. These pre-delayed signals are prepared in advance at known time offsets, allowing the sampling mechanism to directly compare and determine the precise time interval without requiring complex real-time calculations
Solution Approach 2:
A sampling mechanism acts as an intermediary between the delay line and the digital output. This intermediary component captures the instantaneous difference between delayed signal versions, translating the analog time delay information into digital representation with resolution finer than the unit cell delay
Data Source
AI summary
Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.