Interpolation Amplifier Layout for Compact Display Source Drivers
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Solution Overview
Problem
As display panel sizes and resolutions increase, the number of digital bits in image data grows, leading to an exponential increase in the circuit area of decoder circuits, which is not efficiently addressed by existing amplifier interpolation schemes.
Innovation Solution
A source driver with an interpolation amplifier that reduces circuit area and output voltage offset, featuring a digital-to-analog converter, an input selector, and an interpolation amplifier with rail-to-rail structure input circuits, selectively distributing and interpolating voltages based on pixel data bits to generate gradation voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of digital bits in image data is increased to support larger display panels with higher resolutions, then the display quality and resolution are improved, but the circuit area of the decoder circuit is exponentially increased
Solution Approach 1:
The patent segments the image data processing into two parts: upper bits are processed by a decoder circuit to select representative gradation voltages, while lower bits are processed by an interpolation amplifier to generate intermediate voltages. This segmentation reduces the decoder circuit's processing burden and area requirement while maintaining high-resolution output capability.
Solution Approach 2:
The patent introduces an interpolation amplifier as an intermediary component between the decoder circuit and the display panel. This intermediary takes the representative voltages from the decoder and generates additional intermediate voltages, effectively reducing the direct processing requirements of the decoder circuit while maintaining overall output quality.
2Area of stationary object
If existing amplifier interpolation schemes are used to reduce circuit area, then the decoder circuit area is reduced, but the output voltage offset is not effectively minimized
Solution Approach 1:
The patent employs asymmetric transistor sizing in the interpolation amplifier, where transistors in different differential input pairs have different widths ratio. Specifically, the first and third differential input pairs use transistors with a first width ratio, while the second and fourth differential input pairs use transistors with a second width ratio. This asymmetric design compensates for voltage offsets and improves output precision while maintaining compact circuit area.
Solution Approach 2:
The patent changes the width ratio parameter of transistors in different differential input pairs to optimize performance. By adjusting the width ratio as a key parameter, the interpolation amplifier achieves both area reduction and offset minimization, resolving the contradiction between circuit size and voltage precision.
Data Source
AI summary
A source driver includes an interpolation amplifier configured to generate an interpolation voltage based on a received plurality of input voltages and output the interpolation voltage to a display panel; and an input selector configured to receive a first voltage and a second voltage having a different level from the first voltage, and configured to selectively provide at least one of the first and second voltages as the plurality of input voltages in response to some of the lower bits of pixel data. The interpolation amplifier includes four conductive differential input pairs configured to receive four input voltages from among the plurality of input voltages, respectively. Each of the first differential input pair and third differential input pair comprises a first type transistor. Each of the second differential input pair and fourth differential input pair comprises a second type transistor.