Interpolation Filter Architecture for Programmable Multi-Rate Conversion

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Solution Overview

Problem

Existing digital filters for interpolation and decimation, particularly polyphase interpolation filters, are complex and bulky, leading to high area and power overheads, making them challenging to design for programmable interpolation factors and multi-rate data conversion in applications like digital communication and image processing.

Innovation Solution

A device and method that includes a phase delay element, vector magnitude scaling circuitry, adding circuitry, and magnitude compensation scaling circuitry to generate phase-shifted and compensated signals, which are then combined to produce an interpolated output signal, using a simplified architecture that reduces the number of branches and computational requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If polyphase interpolation filters are used to achieve interpolation, then the sampling rate is increased, but the device area and power consumption increase significantly

Engineering Contradiction:
Improvesampling rateVSAvoidfilter area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The polyphase filter bank is segmented into multiple independent polyphase components (e.g., even and odd phases). Each component is processed separately through parallel computation paths, allowing the filter to be implemented with reduced complexity while maintaining the interpolation function. This segmentation enables the filter to achieve higher sampling rates without proportionally increasing the overall device area.

Inventive Principle:
Principle #1Segmentation

2Speed

If polyphase interpolation filters are used to achieve interpolation, then the sampling rate is increased, but the power consumption increases

Engineering Contradiction:
Improvesampling rateVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

By segmenting the filter into polyphase components that can be computed in parallel, the computational workload is distributed efficiently. This reduces the total number of multiplications and additions required compared to a direct implementation, thereby lowering power consumption while achieving the desired sampling rate increase.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The filter implementation uses dynamic resource allocation where computational resources are activated only when needed for each polyphase component. This dynamic approach allows the system to adjust power consumption based on the actual interpolation requirements, preventing unnecessary power usage while maintaining high sampling rates.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If polyphase interpolation filters are designed for programmable interpolation factors, then the adaptability is improved, but the device complexity increases

Engineering Contradiction:
Improveinterpolation factor programmabilityVSAvoidfilter complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The polyphase filter bank is designed with a universal structure that can accommodate different interpolation factors through configuration of the number of polyphase components. The same basic filter architecture can be programmed to achieve different interpolation ratios (e.g., 2x, 3x, 4x) by adjusting which polyphase components are active, providing adaptability without requiring separate dedicated hardware for each interpolation factor.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230299751A1Interpolation filter device, system and method
Publication Date: 2023.09.21 STMICROELECTRONICS INT NV
  • US20230299751A1 patent drawing
  • US20230299751A1 patent drawing
  • US20230299751A1 patent drawing

AI summary

A method generates a delayed signal based on an input signal, and applies vector magnitude scaling to the delayed signal, generating one or more vector magnitude scaled signals. The input signal is added to the one or more vector magnitude scaled signals, generating one or more phase-shifted signals. Compensation scaling is applied to the one or more phase-shifted signals, generating one or more compensated signals. The input signal and the one or more compensated signals are combined, generating an interpolated output signal. The method may be implemented by a device or a system.