Interpolative Clock Synthesis for Wide Range and Low Jitter
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Solution Overview
Problem
Existing clock synthesizers face limitations in frequency coverage and require complex designs and increased costs due to the use of integer dividers and fractional-N dividers, which are costly and occupy significant chip area.
Innovation Solution
The implementation of interpolative dividers, which include a fractional-N divider controlled by a delta-sigma modulator and a phase interpolator, reduces noise by adjusting the phase of the divided signal based on digital quantization errors, allowing for flexible and low-cost clock synthesizer solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If integer dividers are used in PLL synthesizers, then the design is simpler and cost is reduced, but frequency coverage is limited
Solution Approach 1:
The frequency synthesis range is segmented into multiple bands, with each band having a dedicated integer divider configuration. The system switches between different divider configurations to cover the entire frequency range, maintaining simplicity within each band while achieving wide overall coverage.
Solution Approach 2:
The divider configuration is made dynamic by switching between different integer division ratios based on the desired output frequency. This allows the system to adapt to different frequency requirements while maintaining the simplicity of integer division in each operating mode.
2Adaptability or versatility
If fractional-N dividers are used in PLL synthesizers, then frequency coverage is improved, but design complexity and chip area increase
Solution Approach 1:
The complex fractional-N divider circuitry is extracted and replaced with a combination of simple integer dividers and a phase interpolator. The phase interpolator, which is much simpler than a full fractional-N divider, performs the frequency interpolation function, significantly reducing chip area and design complexity.
Solution Approach 2:
Instead of implementing a complex fractional-N divider, the patent uses multiple integer divider paths with different division ratios and combines their outputs through phase interpolation. This copying approach using simpler integer divider circuits achieves the same functional result with reduced complexity.
3Adaptability or versatility
If fractional-N dividers are used in PLL synthesizers, then frequency coverage is improved, but product cost increases
Solution Approach 1:
The patent replaces expensive fractional-N divider circuits with cheaper integer divider circuits and phase interpolators. The simplified architecture using standard integer dividers and basic phase interpolation logic significantly reduces manufacturing cost while maintaining the ability to cover a wide frequency range.
4Adaptability or versatility
If fractional-N dividers are used in PLL synthesizers, then frequency coverage is improved, but jitter is increased
Solution Approach 1:
The patent converts the quantization error from the delta-sigma modulator, which would normally manifest as noise in fractional-N dividers, into a useful phase adjustment signal. The phase interpolator uses this quantization error to fine-tune the phase of the output signal, transforming what would be harmful noise into a beneficial correction mechanism that actually reduces jitter.
Solution Approach 2:
The system implements feedback by using the quantization error from the delta-sigma modulator as a control signal for the phase interpolator. This feedback mechanism allows the system to continuously adjust the output phase to compensate for quantization effects, thereby reducing jitter while maintaining wide frequency coverage.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.