Interpolative Divider Clock Synthesis with Low-Speed Divide-Value Interface
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Solution Overview
Problem
Frequency synthesis using interpolative dividers is limited by the speed of the analog to digital interface between the sigma delta modulator and the fractional-N divider and phase interpolator, which restricts the output frequency and complicates design due to high-speed layout and timing constraints.
Innovation Solution
Implementing a look ahead sigma delta modulator and multiple storage elements to generate and store divide values, with a selector circuit to manage these values, allowing a slower multi-block interface that reduces design complexity and increases output frequency capabilities, including duty cycle control and pulse skipping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high speed interface is used between the sigma delta modulator and the fractional-N divider and phase interpolator, then the output frequency can be higher, but the design complexity increases due to high-speed layout and timing constraints
Solution Approach 1:
The system is divided into multiple blocks: a look ahead sigma delta modulator, multiple storage elements (first and second storage elements), and a selector circuit. This segmentation allows the interface speed to be reduced while maintaining high output frequency capability through parallel data paths and pre-computation of divide values.
Solution Approach 2:
The look ahead sigma delta modulator pre-computes and provides divide values in advance to the storage elements. This preliminary action allows the system to operate with a slower interface speed while still achieving high output frequencies, as the divide values are prepared beforehand rather than computed in real-time during clock cycles.
2Speed
If a high speed interface is used between the sigma delta modulator and the fractional-N divider and phase interpolator, then the output frequency can be higher, but the layout and timing constraints become more stringent
Solution Approach 1:
By segmenting the system into separate blocks with storage elements, the interface speed requirements are relaxed. The layout constraints are reduced because signals do not need to traverse long paths at high speeds, and timing constraints are loosened as the selector circuit can choose from pre-computed values without requiring ultra-precise synchronization.
Solution Approach 2:
The storage elements act as intermediaries between the look ahead sigma delta modulator and the fractional-N divider with phase interpolator. These storage elements buffer the divide values, allowing the interface to operate at lower speeds while maintaining the integrity of the signal transmission and reducing the stringent layout and timing constraints associated with high-speed interfaces.
3Speed
If multiple storage elements are used to store divide values, then the interface speed can be reduced, but the device complexity increases
Solution Approach 1:
The multiple storage elements serve multiple functions: they store divide values generated by the look ahead sigma delta modulator, provide parallel data paths for the selector circuit, and enable duty cycle control by selectively choosing between different stored values. This multi-functionality justifies the increased device complexity by providing additional capabilities beyond simple storage.
Solution Approach 2:
The system changes the parameter of interface speed by using multiple storage elements to buffer data, allowing the interface to operate at lower speeds. The divide values are stored with different parameters (representing different divide ratios), enabling flexible selection to achieve desired output frequencies and duty cycles without requiring high-speed data transmission.
Data Source
AI summary
An interpolative divider includes a look ahead sigma delta modulator circuit to generate divide values according to a divide ratio. A plurality of M storage elements are coupled to the sigma delta modulator to store the divide values, M being at least 2. A selector circuit selects the respective divide values and supplies the divide values to a portion of an interpolative divider circuit, the portion including a divider and a phase interpolator. The interpolative divider generates an output clock signal having a first clock period that may be determined by the first and second divide values. The M storage elements are loaded by a clock signal that is slower than the output clock signal by at least half.