Interpolative Divider Calibration for Low-Jitter PLL Synthesis
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Solution Overview
Problem
Existing clock synthesizers require complex loop filters and voltage-controlled oscillator control, leading to increased design costs and chip area, making them expensive for significant portions of the clock synthesizer market, while seeking low-cost, low-noise, and flexible solutions.
Innovation Solution
A flexible clock synthesizer technique using an interpolative divider that includes a fractional-N divider and a phase interpolator, generating a phase interpolator calibration signal to adjust the phase interpolator output, based on the phase relationship between the reference and feedback clock signals, reducing noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If phase error correction and complex loop filter are used to filter fractional-N noise, then noise is reduced, but device complexity and design cost increase
Solution Approach 1:
The patent extracts the noise filtering function from the complex loop filter and VCO control circuitry, and relocates it to the interpolative divider stage. By correcting phase errors at the divider output before they propagate through the PLL, the system achieves noise reduction without requiring complex loop filters or VCO control mechanisms.
Solution Approach 2:
The patent applies phase error correction preliminarily at the interpolative divider stage, before the signal enters the main PLL loop. By pre-correcting the phase errors introduced by fractional-N division, the system prevents noise propagation through subsequent stages, eliminating the need for complex post-processing filtering.
2Object-affected harmful factors
If phase error correction with offset introduction is used to address jitter, then jitter is reduced, but device complexity and chip area increase
Solution Approach 1:
The patent merges the jitter correction function into the interpolative divider's phase interpolation mechanism. Instead of adding separate offset introduction circuitry, the system uses the existing phase interpolator to directly generate corrected phase signals, achieving jitter reduction without increasing chip area.
3Adaptability or versatility
If fractional-N divider is used to achieve flexible frequency synthesis, then adaptability is improved, but noise and jitter are introduced
Solution Approach 1:
The patent implements feedback through the interpolative divider, where the divided signal is phase-interpolated and fed back to correct the phase errors introduced by fractional-N division. This feedback mechanism continuously compensates for quantization noise while maintaining the flexibility of fractional-N frequency synthesis.
Data Source
AI summary
A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.