Interpolator-Based CDR with Decimated Feedback for Jitter Control
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Solution Overview
Problem
Conventional high-speed data link transceivers face challenges in achieving increased data rates due to high random jitter at the output of clock and data recovery (CDR) circuits, which causes phase shifting of the sampling clock, leading to instability in data communication.
Innovation Solution
An interpolator-based clock and data recovery circuit is introduced, utilizing a de-multiplexer and voting circuit to de-multiplex and decimate feedback signals, which are then digitally filtered to reduce loop dithering and stabilize the sampling clock, enabling higher data rates and reducing random jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR circuits are used, then data communication is maintained, but random jitter increases and phase stability deteriorates at higher data rates
Solution Approach 1:
The feedback signal processing is segmented into multiple parallel paths: a fast path that processes feedback signals without decimation for rapid phase corrections, and a slow path that applies decimation for fine-grained phase adjustments. This segmentation allows the system to handle high data rates while maintaining phase stability by appropriately distributing different types of corrections across the parallel paths.
Solution Approach 2:
The system dynamically switches between different feedback signal processing modes based on operating conditions. At higher data rates, the fast path is activated to maintain responsiveness, while the slow path with decimation is used when fine precision is needed. This dynamic adaptation allows the CDR circuit to maintain reliability across varying data rates.
2Device complexity
If feedback signal processing is simplified, then circuit complexity is reduced, but phase detection precision deteriorates
Solution Approach 1:
The feedback signal processing is divided into two parallel paths with different levels of complexity. The fast path provides coarse phase detection with simpler processing, while the slow path provides fine phase detection with decimation. This segmentation allows the system to achieve high measurement precision without requiring the entire system to be complex, as only the slow path needs the sophisticated decimation logic.
Solution Approach 2:
Instead of applying full decimation to all feedback signals (which would be excessively complex), the system applies decimation only to a subset of feedback signals processed through the slow path. This partial application of the complex processing technique achieves sufficient phase detection precision while keeping overall circuit complexity manageable.
Data Source
AI summary
One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.