Interpolator-Based Clock Recovery for Precise Phase Alignment
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Solution Overview
Problem
Existing data recovery systems face challenges in achieving accurate phase synchronization of clocks, especially as data bit rates increase, due to difficulties in controlling line quality and achieving precise frequency and phase alignment, particularly when transmission frequency changes over time.
Innovation Solution
A data recovery method utilizing an interpolator, a timing loop module, and a data latching circuit, where the interpolator is a programmable delay circuit with a specified delay resolution, separates clock and data paths, and a timing-loop module provides feedback to adjust the phase of the recovered clock to ensure synchronization within a closed-loop system, capable of handling up to ±100 ppm differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated high frequency clock signal is sent along with data signals, then the receiving device can achieve accurate sampling timing, but the system cost increases and line quality becomes difficult to control resulting in errors
Solution Approach 1:
The patent extracts the clock signal transmission from the data transmission channel by sending only a low frequency reference clock separately, while data is transmitted at high speed without a dedicated clock. The receiver regenerates the high frequency clock from the reference clock locally, eliminating the need for high frequency clock transmission over the data line and thus avoiding line quality issues.
Solution Approach 2:
The patent introduces a low frequency reference clock as an intermediary signal that carries timing information without the bandwidth requirements of a high frequency clock. This reference clock serves as a mediator that enables the receiver to reconstruct the high frequency clock waveform through PLL/DLL circuits, thereby achieving accurate sampling without direct high frequency clock transmission.
2Reliability
If a low frequency reference clock is sent and the frequency and phase relationship is regenerated, then transmission cost is reduced, but achieving accurate frequency and phase alignment becomes critical and difficult especially when transmission frequency changes over time
Solution Approach 1:
The patent employs dynamic frequency multiplication and phase adjustment circuits (PLL and DLL) that can adaptively track and regenerate the high frequency clock waveform from a low frequency reference. These circuits dynamically adjust their output frequency and phase to match the transmitted data clock, enabling accurate synchronization even when transmission frequency changes over time.
Solution Approach 2:
The patent implements feedback mechanisms in the PLL and DLL circuits where the regenerated clock output is continuously compared with the incoming data transitions. This feedback allows the circuits to automatically adjust their phase and frequency to achieve optimal alignment, ensuring accurate synchronization despite frequency drift or changes in transmission conditions.
3Measurement precision
If a phase lock loop (PLL) is used to generate the necessary frequency waveform, then frequency regeneration is achieved, but phase alignment is not easily achieved especially if the transmission frequency changes over time
Solution Approach 1:
The patent combines PLL and DLL circuits into an integrated CDR (Clock Data Recovery) system that simultaneously handles both frequency multiplication and phase alignment. This merged architecture allows the system to achieve both accurate frequency regeneration and automatic phase alignment in a unified circuit structure, eliminating the need for separate adjustment mechanisms.
Data Source
AI summary
The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.