Active Interposer Caching for Localized IC Reconfiguration Speed
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Solution Overview
Problem
Programmable integrated circuits face significant challenges in reconfiguration speed and energy consumption, with traditional methods being several orders of magnitude slower than desired and requiring costly silicon real estate for on-chip caching and energy-intensive off-chip fetching of configuration bit-streams.
Innovation Solution
A system comprising a host processor, integrated circuit package with an active interposer and auxiliary chip, where memory elements on both components store configuration data, enabling faster reconfiguration through sequential loading and caching of configuration bit-streams, and utilizing through silicon vias and microbumps for efficient communication, along with optional decryption/decompression circuitry for optimized data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If configuration data is stored in off-chip memory and fetched via the configuration circuit chain, then device complexity is reduced, but reconfiguration speed becomes several orders of magnitude slower than desired
Solution Approach 1:
The patent introduces a third dimension for configuration data storage by placing memory elements on a separate interposer substrate beneath the programmable device, rather than integrating memory on the same chip plane. This spatial separation allows independent optimization of logic and memory functions while enabling faster parallel access paths through through-silicon vias (TSVs) that penetrate vertically through the interposer substrate.
Solution Approach 2:
The interposer substrate acts as an intermediary component between the programmable device and off-chip memory, providing localized memory elements and TSV-based communication paths. This intermediary structure enables faster configuration data transfer by creating a dedicated, short-distance communication channel that bypasses the slower conventional configuration circuit chain.
2Speed
If on-chip caching of configuration bit-streams is implemented to hide reconfiguration latency, then reconfiguration speed improves, but silicon real estate cost increases undesirably
Solution Approach 1:
The patent segments the configuration storage function across multiple locations: a portion of configuration data is cached in memory elements on the interposer substrate directly beneath the programmable device, while the remaining configuration data resides in off-chip memory. This segmentation allows the critical path configuration data to be locally cached without requiring complete on-chip storage, thus reducing silicon real estate requirements while still achieving faster reconfiguration.
Solution Approach 2:
The patent implements local caching by placing memory elements specifically on the interposer substrate beneath the programmable device, creating a localized cache for configuration data. This local quality approach ensures that frequently accessed configuration data is stored close to the logic elements that need it, reducing access latency without requiring global on-chip caching across the entire device.
3Device complexity
If configuration bit-streams are repeatedly fetched from off-chip storage via the configuration circuit chain, then device complexity is maintained, but energy consumption increases significantly
Solution Approach 1:
The patent implements preliminary action by pre-loading configuration data into memory elements on the interposer substrate before it is needed by the programmable device. The interposer memory acts as a buffer that is populated in advance, allowing the programmable device to quickly access pre-positioned configuration data without repeatedly fetching from off-chip storage, thus reducing energy consumption.
Solution Approach 2:
The interposer substrate with its local memory elements serves as an intermediary that reduces energy consumption by providing a intermediate storage layer between off-chip memory and the programmable device. Configuration data is transferred once to the interposer memory and then accessed locally multiple times, eliminating the need for repeated high-energy transfers through the configuration circuit chain.
Data Source
AI summary
A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.