Interposer Bonding for 3D NAND Wafer Warpage Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating 3D NAND memory devices is the difficulty in achieving sufficient bonding strength and precise alignment due to wafer warpage and high precision requirements in direct bonding processes, which increases costs and reduces production yield.
Innovation Solution
The use of an interposer structure with interposer bonding layers and redistribution layers that include adhesive materials like epoxy, providing improved bonding strength and flexibility to adjust for wafer deformation, while allowing for relaxed lithography alignment and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If direct bonding process is used for 3D NAND memory devices, then bonding strength can be achieved, but wafer warpage and high precision requirements increase costs and reduce production yield
Solution Approach 1:
The patent introduces an interposer structure as an intermediary component between the first and second semiconductor structures. This interposer includes bonding layers with bonding contacts that facilitate alignment and bonding, acting as a mediator that absorbs misalignment and reduces the precision requirements for direct bonding between the main semiconductor wafers.
Solution Approach 2:
The bonding interface is segmented into multiple components: the interposer structure with its own bonding layers and contacts, separate from the main semiconductor structures. This segmentation allows the bonding process to be divided into stages, with the interposer serving as a buffer that compensates for warpage and alignment variations.
2Strength
If direct bonding process is used for 3D NAND memory devices, then bonding strength can be achieved, but costs increase due to high precision requirements
Solution Approach 1:
The interposer structure serves as a cost-effective intermediary that simplifies the bonding process. By introducing this intermediate component with integrated bonding layers, the patent reduces the need for expensive high-precision alignment equipment and processes, thereby lowering manufacturing costs while maintaining bonding strength.
3Strength
If interposer structure with adhesive materials is used, then bonding strength and flexibility are improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the interposer structure: mechanical support, electrical connection through conductive contacts, and bonding through adhesive bonding layers. By combining these functions into a single integrated component, the patent reduces overall system complexity compared to using separate components for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances critical dimension control, increases production yield, and reduces costs by improving bonding strength and electrical connections between semiconductor structures, facilitating easier alignment and bonding.
Implementation Method 1
The interposer structure includes a first interposer bonding layer having a plurality of first interposer contacts disposed at a first side of the interposer structure, and a second interposer bonding layer having a plurality of second interposer contacts disposed at a second side opposite of the first side of the interposer structure
Data Source
AI summary
A method for forming a three-dimensional (3D) memory device includes the following operations. First, in a first semiconductor structure, logic process-compatible devices and first bonding contacts are formed conductively connected to the logic process-compatible devices. In a second semiconductor structure, an array of NAND memory cells and second bonding contacts are formed conductively connected to the array of NAND memory cells. A first surface of an interposer structure is bonded to the second semiconductor structure. First interposer contacts disposed at the first surface of the interposer structure are conductively connected to the second bonding contacts. A second surface of the interposer structure is bonded to the first semiconductor structure. Second interposer contacts disposed at the second surface of the interposer structure are conductively connected to the first bonding contacts. The interposer structure is attached to the first semiconductor structure and the second semiconductor structure.