Interposer Bridge Packaging With Vertical Links for Low-Delay Stacking
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Solution Overview
Problem
Current heterogeneous integration solutions for semiconductor packaging struggle to achieve high performance, small area, and low cost, particularly in mobile terminals where high transmission bandwidth and low transmission delay are required.
Innovation Solution
The proposed semiconductor packaging structure incorporates a device package with a substrate, device circuit, vertical conductive elements, and a molding layer, along with stacked memory packages. This configuration uses vertical conductive elements to connect the device package and memory packages, eliminating the need for etching holes in the molding layer and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vertical conductive elements are used to connect device package and memory packages, then manufacturing cost is reduced and manufacturing complexity is simplified, but transmission bandwidth and transmission delay performance must be maintained
Solution Approach 1:
The patent transitions from traditional lateral/horizontal interconnection methods to vertical conductive elements for stacking packages. This dimensional change enables Package-on-Package architecture where memory packages are stacked vertically on the device package, reducing footprint area while maintaining connection efficiency and enabling high-bandwidth vertical signal paths
2Area of stationary object
If packages are stacked to reduce area, then package area is reduced, but transmission delay must be kept low
Solution Approach 1:
By stacking packages in the vertical dimension rather than expanding horizontally, the patent achieves high integration density without increasing lateral footprint. The vertical stacking with direct conductive connections minimizes signal path length compared to lateral routing, thereby reducing transmission delay despite the stacked configuration
Solution Approach 2:
The patent implements Package-on-Package stacking where memory packages are positioned on top of the device package, creating a nested vertical arrangement. This nesting approach consolidates multiple functional packages into a compact vertical structure, reducing overall package area while maintaining short inter-package connection paths
3Reliability
If heterogeneous integration is implemented to achieve high performance, then transmission bandwidth is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the integrated system into separate functional packages (device package and memory packages) that are manufactured independently using optimized processes for each function, then stacked and connected vertically. This segmentation allows each package to be manufactured with specialized processes without requiring complex heterogeneous integration of different device types in a single manufacturing flow
Solution Approach 2:
The patent uses standard package interfaces and vertical conductive elements as intermediary connection structures between the device package and memory packages. These standardized interfaces simplify the integration process by providing uniform connection protocols and mechanical interfaces, reducing manufacturing complexity despite the heterogeneous nature of the stacked packages
Data Source
AI summary
In certain aspects, a semiconductor packaging structure includes an interposer structure, which includes an interconnect bridge, a device circuit, a set of conductive elements, and a molding layer. The interconnect bridge includes a stack of conductive layers and dielectric layers that are disposed alternately and an interconnect structure formed in the stack and penetrating at least part of the stack to connect to a conductive layer in the stack. The device circuit is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on and coupled to the interconnect bridge. The set of conductive elements is disposed on a periphery of the device circuit. The interconnect structure of the interconnect bridge is connected to at least one conductive element from the set of conductive elements. The molding layer encapsulates the device circuit and the set of conductive elements.