Interposer IC Package Buffer Layer for Encapsulation Edge Stress
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Solution Overview
Problem
The integration of high-density electronic components in semiconductor wafers faces challenges due to excessive stress at the edges of integrated circuit devices during encapsulation, which can lead to delamination and damage, particularly when using materials with high Young's modulus and coefficient of thermal expansion.
Innovation Solution
The implementation of stress buffer layers made of a polymer material with specific properties, including a lower Young's modulus and higher coefficient of thermal expansion than the encapsulant, around the integrated circuit devices to mitigate stress and prevent damage during high-temperature expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density integration is achieved through repeated reductions in minimum feature size, then integration density improves, but the area occupied by components decreases and bonding capability deteriorates
Solution Approach 1:
The patent transitions from 2D planar integration to 3D vertical stacking by introducing interposers that enable multiple chips to be stacked vertically. This dimensional change allows continued increase in integration density without further reduction in feature size, while the interposer provides a larger bonding area to compensate for the reduced chip area.
Solution Approach 2:
The interposer serves as an intermediary component between chips, providing redistribution of ball contact areas from the small chip surface to a larger interposer surface. This mediator enables bonding capability to be maintained or improved despite the reduction in chip area resulting from high-density integration.
2Stress or pressure
If stress buffer layers with lower Young's modulus are used around integrated circuit devices, then stress during encapsulation is reduced, but device complexity increases
Solution Approach 1:
Stress buffer layers are applied locally around integrated circuit devices rather than uniformly across the entire package. This localized application provides stress relief precisely where needed at device edges during encapsulation, while minimizing the overall added complexity of the package structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress buffer layers effectively reduce stress at the outer edges of integrated circuit devices, enhancing the yield and reliability of the integrated circuit packages by absorbing thermal expansion without causing delamination or damage.
Implementation Method 1
the stress buffer layers effectively reduce stress at the outer edges of integrated circuit devices, enhancing the yield and reliability of the integrated circuit packages by absorbing thermal expansion without causing delamination or damage
Data Source
AI summary
In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.