Interposer Bump Layout for Coplanarity Improvement
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Solution Overview
Problem
As semiconductor devices integrate more components into smaller areas, maintaining coplanarity of conductive bumps on interposers becomes increasingly difficult, leading to issues like cold-joints and bridging, which lower manufacturing yield and reliability.
Innovation Solution
Adjusting the size and pitch of conductive bumps in regions with varying pattern densities by increasing the cross-sectional area of bumps in low and medium pattern density regions and adding dummy bumps to match the pitch of high pattern density regions, thereby reducing height differences and improving coplanarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but maintaining coplanarity of conductive bumps becomes increasingly difficult
Solution Approach 1:
The patent applies local quality by differentiating bump pitch specifications across different regions of the interposer. High pattern density regions maintain smaller bump pitches while low pattern density regions use larger bump pitches. This regional differentiation allows each area to be optimized independently, maintaining coplanarity where needed while preserving integration density overall.
Solution Approach 2:
The patent changes the pitch parameter of conductive bumps based on regional pattern density. By adjusting the pitch parameter dynamically across different regions rather than using a uniform pitch, the system maintains coplanarity in critical areas while still achieving high integration density through optimized component placement in other areas.
2Ease of manufacture
If uniform bump pitch is used across all regions, then manufacturing is simpler, but coplanarity deteriorates in low pattern density regions leading to cold-joints and bridging
Solution Approach 1:
The patent implements local quality by specifying different bump pitch requirements for different regions. High pattern density regions use smaller pitches while low pattern density regions use larger pitches. This regional customization improves reliability by preventing coplanarity issues in low density areas while maintaining manufacturing feasibility through clear regional guidelines.
Solution Approach 2:
The patent segments the interposer surface into distinct regions based on pattern density characteristics. By dividing the manufacturing area into high density and low density zones with different bump pitch specifications, the system addresses coplanarity issues locally without requiring complete redesign of the entire bump layout, thus improving reliability while maintaining ease of manufacture.
3Reliability
If bump pitch is reduced to improve coplanarity in low pattern density regions, then reliability improves, but manufacturing complexity increases due to varying pitch requirements
Solution Approach 1:
The patent applies local quality by implementing region-specific bump pitch specifications rather than uniform pitch across the entire interposer. This approach improves coplanarity and reliability in low pattern density regions while maintaining simpler, smaller pitches in high density regions. The complexity is localized to specific areas rather than affecting the entire device.
Solution Approach 2:
The patent segments the bump layout into distinct regions with different pitch characteristics. This segmentation allows each region to be optimized independently for its specific pattern density requirements, improving overall reliability without requiring complex variable pitch designs across the entire device. The segmented approach manages complexity by creating clear regional boundaries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor devices by reducing coplanarity issues, avoiding cold-joints and bridging, and increasing production yield while maintaining high electro-plating speed and reducing manufacturing costs.
Implementation Method 1
maintaining high electro-plating speed
Data Source
AI summary
A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.