Si Interposer Capacitor Arrays With Redundancy for Yield Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The failure of a single capacitor in Si interposer layers used in advanced 2.5D and/or 3D IC devices can jeopardize the accuracy of final target capacitors and impact overall yield, highlighting the need for a solution to address capacitor reliability.
Innovation Solution
Incorporating redundant capacitor arrays in the Si interposer layer, which are connected in series or parallel with regular capacitor arrays, to provide backup and ensure continued functionality even if some capacitors fail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant capacitor arrays are added to the interposer layer, then reliability and yield are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The capacitor arrays are segmented into regular capacitor arrays and redundant capacitor arrays, which are separately formed and then connected through conductive layers. This segmentation allows the redundant arrays to be independently formed and connected, managing the complexity while providing backup functionality.
Solution Approach 2:
The redundant capacitor arrays are formed in advance during the manufacturing process, before final assembly. The conductive layers are prepared to connect both regular and redundant arrays, so that if a regular capacitor fails, the redundant one can be activated without requiring additional manufacturing steps.
2Productivity
If redundant capacitor arrays are added to the interposer layer, then yield is improved, but manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is segmented into forming regular capacitor arrays and forming redundant capacitor arrays as separate but parallel processes. Both arrays use the same formation techniques and materials, allowing standardized manufacturing procedures that maintain precision while producing multiple capacitor sets.
Solution Approach 2:
Both regular and redundant capacitor arrays use identical dielectric layers, electrode structures, and formation processes. This homogeneity ensures that manufacturing precision requirements are consistent across all capacitors, simplifying quality control and process management.
3Object-generated harmful factors
If oxide layer is added to isolate upper electrodes, then signal integrity is improved, but device complexity increases
Solution Approach 1:
An oxide layer is introduced as an intermediary between the upper electrodes of regular and redundant capacitor arrays. This oxide layer acts as an insulating barrier that prevents electrical leakage and signal interference between adjacent capacitors, while the top conductive layer serves as a mediator to connect all upper electrodes together.
Solution Approach 2:
The top conductive layer serves multiple functions: it connects all upper electrodes (both regular and redundant) together, provides a common electrical node, and works in conjunction with the oxide layer to ensure proper electrical isolation where needed while maintaining electrical connectivity where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of redundant capacitor arrays enhances the reliability and accuracy of capacitors in semiconductor devices, improving yield and reducing signal noise and leakage between IC devices.
Implementation Method 1
The oxide layer isolates the upper electrode of each regular capacitor and the upper electrode of each redundant capacitor
Implementation Method 2
Each regular capacitor includes a lower electrode, a dielectric layer, and an upper electrode, wherein the dielectric layer is surrounded by the lower electrode, and the upper electrode is surrounded by the dielectric layer
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes a package substrate, an interposer layer, an oxide layer, and a top conductive layer. The interposer layer is disposed on the package substrate. The interposer layer includes a plurality of regular capacitor arrays and a plurality of redundant capacitor arrays. The regular capacitor arrays are located in the interposer layer, wherein each regular capacitor array includes a plurality of regular capacitors. Each regular capacitor includes a lower electrode, a dielectric layer, and an upper electrode, wherein the dielectric layer is surrounded by the lower electrode, and the upper electrode is surrounded by the dielectric layer. The redundant capacitor arrays are located in the interposer layer and located around the regular capacitor arrays, wherein each redundant capacitor array includes a plurality of redundant capacitors.