Interposer Capacitor Electrode Area vs Routing Complexity
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Solution Overview
Problem
Conventional interposers face issues when capacitors and rewiring layers are formed together, leading to various problems in their functionality and performance.
Innovation Solution
A novel interposer design featuring a capacitor formed on nearly the entire substrate surface with specific electrode and dielectric layer configurations, along with through-hole conductors and via conductors for power supply, ground, and signal connections, which allows for efficient electrical connectivity between a semiconductor chip and a package substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a capacitor and a rewiring layer are formed together on an interposer, then the interposer can provide both decoupling function and rewiring function, but the capacitor electrodes cannot occupy the entire substrate surface due to space constraints for routing patterns
Solution Approach 1:
The patent divides the interposer into distinct functional regions: a first surface dedicated to capacitor electrode formation and a second surface for routing patterns. This spatial segmentation allows the capacitor electrodes to occupy nearly the entire first surface while routing patterns are confined to the second surface, resolving the space conflict between large-area capacitor electrodes and routing patterns.
Solution Approach 2:
The patent utilizes the third dimension by forming capacitor electrodes on one surface of the substrate and routing patterns on the opposite surface. This dimensional separation allows both the capacitor electrodes to occupy maximum area on the first surface and routing patterns to be laid out on the second surface without spatial interference, effectively resolving the area-complexity contradiction.
2Reliability
If the capacitor electrode area is increased to improve decoupling capacity, then the noise absorption capability is enhanced, but the available space for forming routing patterns is reduced
Solution Approach 1:
The patent segments the substrate into two distinct surfaces with dedicated functions: the first surface is optimized for capacitor electrode formation to maximize decoupling capacity and noise absorption, while the second surface is dedicated to routing patterns. This segmentation allows the capacitor electrodes to occupy nearly the entire first surface area, maximizing noise absorption capability without compromising routing pattern space.
Solution Approach 2:
By placing capacitor electrodes on the first surface and routing patterns on the second surface (opposite dimension), the patent enables the capacitor electrodes to expand to occupy nearly the entire first surface area, thereby maximizing decoupling capacity and noise absorption capability while maintaining adequate space for routing patterns on the opposite surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interposer effectively forms a decoupling capacitor with a large capacity, absorbing noise and enabling efficient signal transmission, while allowing for the formation of capacitor electrodes with a large area without occupying the surface with rewiring patterns.
Implementation Method 1
a capacitor comprising lower electrodes 18, a dielectric layer 16, and upper electrodes 14
Implementation Method 2
a dielectric layer 16 formed on nearly the entire surface of one face of the silicon substrate 12
Implementation Method 3
through-hole conductors 20 for power supply, through-hole conductors 20 for ground, through-hole conductors 20 for signal, via conductors 22 for power supply, via conductors 22 for ground
Data Source
AI summary
Means for Solution: This interposer (10) comprises the silicon substrate (12), a plurality of through-hole conductors (20) formed on the above-described silicon substrate, and a capacitor (15) formed with the upper electrodes (14) and the lower electrodes (18) formed by extending the land portions of the above-described through-hole conductors and the dielectric layer (16) formed between the both electrodes. The rewiring layers (23-1, 23-2) formed as desired are formed on the layers other than the above-described capacitor layer.