Interposer Capacitors for Supply Voltage Noise Reduction

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Solution Overview

Problem

High-frequency voltage ripple in integrated circuit power supply voltages poses a challenge due to parasitic inductance in stacked die assemblies, which can reach unacceptable levels, impacting both analog and digital circuits.

Innovation Solution

Incorporating capacitors in an interposer coupled to the supply and ground planes of a substrate, which are then connected to the integrated circuit die, provides effective capacitance to reduce noise, eliminating the need for costly embedded capacitors on the IC die and minimizing semiconductor real estate usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If capacitors are embedded on the IC die, then noise reduction effectiveness is improved, but semiconductor real estate consumption increases and manufacturing cost increases

Engineering Contradiction:
Improvevoltage rippleVSAvoidIC die area
Core Design Contradiction:
Object-affected harmful factorsVSArea of moving object

Solution Approach 1:

The patent extracts the capacitor function from the IC die and relocates it to the interposer substrate. This allows the IC die to maintain its original area while the noise reduction functionality is provided by capacitors on the interposer, which is electrically connected to the die through supply and ground planes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The interposer acts as an intermediary between the IC die and the external circuitry. By placing capacitors on the interposer and connecting them to the IC die through supply and ground planes, the system achieves noise reduction without modifying the IC die itself, thus preserving semiconductor real estate.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If parasitic inductance is reduced, then noise reduction effectiveness is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage rippleVSAvoidstacked die assembly complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the power delivery function with the noise reduction function by integrating capacitors into the interposer's supply and ground plane structure. This unified approach provides both power distribution and voltage ripple filtering while managing parasitic inductance, rather than treating them as separate concerns that would increase complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces high-frequency voltage ripple by delivering capacitance directly to the IC die, improving noise reduction without consuming valuable IC die space and enhancing the effectiveness of noise filtering.

Implementation Method 1

The interposer includes a plurality of capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where the plurality of capacitors of the interposer provide capacitance to the first integrated circuit die

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9337138B1Capacitors within an interposer coupled to supply and ground planes of a substrate
Publication Date: 2016.05.10 XILINX INC
  • US9337138B1 patent drawing
  • US9337138B1 patent drawing
  • US9337138B1 patent drawing

AI summary

An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.