Interposer Carrier Wafer Support for 3D IC Thinning
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Solution Overview
Problem
The fabrication and assembly of thin interposers in 3D IC packaging face challenges such as limited processing temperatures due to low-melting-temperature adhesives, increased wafer breakage, and warpage issues, which affect the reliability of microbumps and solder bumps.
Innovation Solution
The use of a carrier wafer that becomes an integral part of the mechanical structure, providing support during thinning processes without low-melting-temperature adhesives, and utilizing wafer-to-wafer bonding to minimize thermal stress, along with the formation of cavities and electroconductive contacts for die encapsulation and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If thin interposers are fabricated and assembled using low-melting-temperature adhesive carriers, then the interposer thickness is reduced to achieve smaller form factors, but the maximum processing temperature is limited and wafer breakage increases
Solution Approach 1:
The interposer fabrication process is segmented into two distinct phases: first, thick interposers are fabricated on carrier wafers using high-temperature processing; second, the interposers are thinned to final thickness after assembly. This segmentation allows each phase to use optimal processing conditions without compromise.
Solution Approach 2:
All high-temperature processing, including semiconductor device fabrication and interposer formation, is performed preliminarily while the interposer is still thick and supported by the carrier wafer. This preliminary action enables use of high temperatures that would be impossible during final thin interposer assembly.
2Volume of moving object
If thin interposers are assembled onto carrier wafers with temporary adhesives, then the interposer can be thinned to desired thickness, but warpage issues occur during assembly that create stress on solder bumps and functional dies
Solution Approach 1:
The conventional sequence is inverted: instead of thinning the interposer before assembly, the interposer is assembled in its thick state and then thinned after assembly. This inversion eliminates warpage because the thick interposer provides structural stability during assembly, and thinning occurs only after the interposer is securely bonded to the substrate.
Solution Approach 2:
The carrier wafer provides beforehand cushioning and mechanical support during all high-stress processing operations. This support prevents warpage and stress accumulation during fabrication and assembly, with the carrier being removed only after the interposer is fully processed and thinned.
3Manufacturing precision
If low-melting-temperature adhesives are used to mount ITP wafers on carriers during thinning, then the thinning process can proceed, but the maximum processing temperature is limited by the adhesive melting point
Solution Approach 1:
All high-temperature processing operations are performed preliminarily while the interposer is still mounted on the carrier wafer. This includes semiconductor device fabrication, metallization, and other thermal processes that require temperatures well above what would be tolerable with temporary adhesives present.
Solution Approach 2:
The carrier wafer and temporary adhesive are extracted and removed from the system after all high-temperature processing is complete. This extraction allows the interposer to be thinned to final thickness without the temperature constraints that would otherwise be imposed by adhesive presence throughout the entire process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wafer breakage and warpage issues, allowing for more reliable and stress-free assembly of 2D and 3D IC packages with improved thermal matching and structural integrity.
Implementation Method 1
The use of a carrier wafer that becomes an integral part of the mechanical structure, providing support during thinning processes
Implementation Method 2
utilizing wafer-to-wafer bonding to minimize thermal stress
Implementation Method 3
a dielectric material is disposed in the cavity so as to encapsulate the first die
Data Source
AI summary
An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.