Interposer Cavity Layout for Thinner 3D Chip Packages
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Solution Overview
Problem
Existing semiconductor packaging techniques have limitations in achieving smaller, more efficient package structures while maintaining effective electrical connections and protection for semiconductor devices, particularly in 3D-IC devices, leading to challenges in reducing package size and improving electrical performance.
Innovation Solution
The development of a 3D packaging process involving a package substrate with laminated insulating layers and conductive features, an interposer substrate with through-vias and a redistribution layer, and semiconductor devices bonded via conductive structures, along with underfill elements and a protective layer, to form a chip-on-wafer-on-substrate package structure that reduces package size and enhances electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging techniques are used, then package structure provides protection and connection interface, but package size and height cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from conventional 2D packaging to 3D packaging by stacking multiple semiconductor devices vertically on the interposer substrate. This dimensional change allows multiple devices to be integrated within a smaller footprint area, reducing overall package size while maintaining connection integrity through vertical interconnect structures.
Solution Approach 2:
The patent implements nesting by placing semiconductor devices within cavities formed in the interposer substrate. The devices are embedded into these recessed regions, allowing the package structure to accommodate components in a nested configuration that minimizes external dimensions while preserving functional connections.
2Area of stationary object
If package structure is reduced in size, then smaller footprint is achieved, but electrical performance and signal quality deteriorate due to increased RC delay and noise
Solution Approach 1:
The interposer substrate serves as an intermediary component between the semiconductor devices and the external package substrate. It provides dedicated interconnect structures including through-substrate vias and redistribution layers that mediate electrical signals, maintaining signal quality and reducing RC delay despite the compacted footprint achieved through 3D stacking.
Solution Approach 2:
The patent segments the electrical connection path into multiple dedicated layers within the interposer substrate, with separate routing layers for different signal types. This segmentation allows optimized signal paths for each function, reducing crosstalk and noise while maintaining small overall footprint through vertical integration.
3Productivity
If multiple semiconductor devices are integrated in 3D configuration, then functional density increases, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent employs preliminary action by pre-forming cavities in the interposer substrate before device attachment, and by pre-attaching semiconductor devices to the interposer in a controlled sequence. This staged approach simplifies the overall manufacturing process compared to attempting to assemble multiple devices simultaneously, making the 3D integration process more manageable despite increased functional density.
Solution Approach 2:
The interposer substrate acts as a mediator that simplifies the integration of multiple semiconductor devices. It provides standardized attachment surfaces and pre-configured interconnect structures that reduce the complexity of direct device-to-device interconnections, enabling higher functional density while keeping the manufacturing process relatively streamlined.
Data Source
AI summary
A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed over the package substrate and includes a silicon substrate. The interposer substrate has a bottom surface facing and adjacent to the package substrate, a top surface opposite the bottom surface, and a cavity formed on the top surface. The first semiconductor device is disposed on the top surface of the interposer substrate. The second semiconductor device is received in the cavity and electrically connected to the first semiconductor device and/or the interposer substrate.