Interposer Cavity Packaging for Thin, Reliable Chip Adhesion
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Solution Overview
Problem
Current semiconductor package structures face challenges in achieving reliable adhesion between interposer substrates and semiconductor chips, particularly in maintaining strong bonding while minimizing thickness and ensuring electrical connectivity.
Innovation Solution
A semiconductor package structure is designed with an interposer substrate featuring a cavity recessed from its lower surface, where the semiconductor chip is positioned, and an adhesive layer is applied on all upper and side surfaces of the chip, enhancing adhesion and electrical connectivity through connection bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an adhesive layer is applied only on the lower surface of the semiconductor chip, then the manufacturing process is simpler, but the adhesion reliability between the interposer substrate and the semiconductor chip is insufficient
Solution Approach 1:
The adhesive layer is extended from the traditional two-dimensional application on the lower surface only to a three-dimensional configuration covering the lower surface and side surfaces of the semiconductor chip. This dimensional expansion ensures complete contact between the adhesive layer and the chip, preventing delamination at the sides and significantly improving adhesion reliability.
Solution Approach 2:
The interposer substrate includes a cavity that receives the semiconductor chip, with the adhesive layer positioned both inside the cavity (on the lower surface of the chip) and outside the cavity (on the side surfaces of the chip). This nested configuration allows the adhesive layer to comprehensively bond the chip to the interposer substrate, ensuring reliable adhesion while maintaining a compact stacked structure.
2Length of stationary object
If the semiconductor package structure uses a thick interposer substrate without cavity, then the structural strength is higher, but the overall thickness of the package increases
Solution Approach 1:
A cavity is extracted from the interposer substrate to create a recessed region that accommodates the semiconductor chip. This cavity removes unnecessary material from the interposer substrate, reducing the overall package thickness while maintaining structural integrity through the strategic placement of the cavity away from critical load-bearing regions.
Solution Approach 2:
The interposer substrate transitions from a flat, two-dimensional structure to a three-dimensional structure with a cavity. This dimensional change allows the substrate to provide structural strength while creating space for the chip, thereby reducing the overall package thickness without compromising mechanical support.
3Reliability
If the adhesive layer covers all upper and side surfaces of the semiconductor chip, then the adhesion reliability is maximized, but the amount of adhesive material required increases
Solution Approach 1:
The cavity in the interposer substrate serves as a container that holds the semiconductor chip and the adhesive layer. By nesting the chip within the cavity, the adhesive layer is confined to specific regions (lower surface and side surfaces) rather than requiring coverage of the entire chip perimeter, optimizing material usage while ensuring complete adhesion contact.
Solution Approach 2:
The adhesive layer is applied selectively to the lower surface and side surfaces of the semiconductor chip where adhesion is most critical for structural integrity. This localized application strategy ensures maximum bonding strength at the interface between the chip and interposer substrate while minimizing the total quantity of adhesive material required.
4Reliability
If connection bumps are arranged only at the corners of the semiconductor chip, then the manufacturing process is simpler, but the electrical connectivity and mechanical support are insufficient
Solution Approach 1:
Connection bumps are strategically positioned at the corners of the semiconductor chip, where they provide optimal electrical connectivity and mechanical support. This corner-specific arrangement leverages the geometric properties of the chip to achieve maximum bonding efficiency and electrical performance with a minimal number of bumps, simplifying the manufacturing process while ensuring reliable connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves adhesion reliability and reduces the overall thickness of the semiconductor package while maintaining effective electrical connections, enabling efficient stacking and integration of semiconductor chips.
Implementation Method 1
an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip
Data Source
AI summary
A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.