Interposer Cavity for Capacitor Placement
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Solution Overview
Problem
Existing interposers face challenges in effectively reducing high-frequency power supply noise due to limited capacitor placement, which degrades power supply capability and signal wiring, and previous solutions with high dielectric materials between power and ground layers result in insufficient capacitance.
Innovation Solution
An interposer with a substrate featuring penetrating electrodes, multilayer wiring, and UBM structures, allowing capacitors to be mounted close to electronic parts, with exposed wiring layers and bumps connected to electrode pads, forming a power supply path equivalent to one without cavity portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If capacitors are mounted on peripheral areas or back side of electronic parts, then capacitor placement is possible, but the distance between capacitor and electronic part is too large to effectively reduce high-frequency power supply noise
Solution Approach 1:
The patent utilizes the vertical dimension by forming a cavity portion that extends from the back surface of the interposer toward the middle of the wiring layer, allowing capacitors to be mounted in three-dimensional space rather than only on the two-dimensional peripheral areas. This enables capacitor placement much closer to the electronic part while maintaining effective power supply noise reduction.
Solution Approach 2:
The cavity portion is formed within the interposer structure, nesting the capacitor mounting space inside the interposer body. This nested configuration allows the capacitor to be positioned in the cavity portion close to the electronic part mounting surface, achieving short distance connection without occupying peripheral mounting areas.
2Length of moving object
If a cavity is formed from the back surface of the interposer to the middle of the wiring layer to mount capacitor closer, then capacitor can be disposed at position closer than electronic part, but the wiring path across wiring layers is broken and power supply capability is reduced
Solution Approach 1:
The cavity portion is configured to extend only to the middle of the wiring layer rather than through the entire interposer thickness, segmenting the cavity depth to avoid complete interruption of power supply paths. This partial penetration approach maintains wiring continuity while enabling capacitor placement closer to the electronic part.
Solution Approach 2:
The cavity portion acts as an intermediary space that accommodates the capacitor while allowing power supply wiring to pass through or around it. The wiring layer is configured to provide power supply paths that bypass the cavity portion, using the cavity as a mediator space rather than a complete barrier.
3Ease of manufacture
If high dielectric material is sandwiched between power supply layer and ground layer to form capacitor sheet, then capacitor structure is integrated, but the capacitance is too small to sufficiently reduce power supply noise
Solution Approach 1:
Instead of relying solely on thin high dielectric material between wiring layers for capacitance, the patent utilizes the vertical depth of the cavity portion to accommodate larger external capacitors. This three-dimensional approach provides sufficient capacitance value while maintaining integrated manufacturing through the cavity formation process.
Data Source
AI summary
An interposer includes a substrate includes a plurality of penetrating electrodes, and a wiring portion formed on the substrate, in which the wiring portion includes a wiring layer electrically connected to the penetrating electrodes and an insulating layer covering the wiring layer. The interposer includes a plurality of first UBM structures provided at a side opposite the substrate of the wiring portion, in which the first UBM structures are electrically connected to the wiring layer. The interposer includes a plurality of bumps provided at the side opposite the wiring portion of the substrate, in which the plurality of bumps is electrically connected to each of the penetrating electrodes via a plurality of second UBM structures.