Interposer Cavity Package Structure for Lower PoP Height and Heat Dissipation

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Solution Overview

Problem

The increasing integration and miniaturization of semiconductor chips lead to higher mounting heights and thermal resistance in package-on-package structures, which can hinder mounting on PCBs and reduce durability and reliability.

Innovation Solution

A semiconductor package design with a cavity in the interposer and conductive connecting bodies to minimize mounting height and improve heat dissipation, utilizing an underfilling film to fill gaps and enhance electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If package-on-package structure is used to achieve high integration, then integration level is improved, but mounting height increases

Engineering Contradiction:
Improveintegration levelVSAvoidmounting height
Core Design Contradiction:
Adaptability or versatilityVSLength of moving object

Solution Approach 1:

The cavity in the interposer allows one package to be nested within the structural footprint of another package, enabling vertical stacking while reducing the overall mounting height by utilizing the cavity space for heat dissipation and structural integration

Inventive Principle:
Principle #7Nested doll (Nesting)

2Strength

If solders are used to join individual packages, then connection strength is improved, but thermal resistance increases

Engineering Contradiction:
Improveconnection strengthVSAvoidthermal resistance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The cavity extracts the heat generation issue from the traditional solder joint interface by providing a dedicated space filled with thermally conductive material, separating the mechanical connection function from the thermal management function and significantly reducing thermal resistance

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The cavity is filled with thermally conductive material that creates a composite structure between the interposer and package substrates, combining mechanical support with superior thermal conduction properties to simultaneously achieve connection strength and low thermal resistance

Inventive Principle:
Principle #40Composite materials

3Adaptability or versatility

If gap is formed between packages by solders, then connection flexibility is improved, but heat dissipation worsens

Engineering Contradiction:
Improveconnection flexibilityVSAvoidheat dissipation
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The cavity, which could be seen as an empty space or defect, is converted into a beneficial thermal management feature by filling it with thermally conductive material, transforming potential heat trapping into an effective heat dissipation pathway

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Minimizes mounting height, increases durability and reliability by improving heat dissipation, and facilitates easy gap filling between packages.

Implementation Method 1

an underfilling film configured to fill a gap between the interposer at the cavity and the second package substrate

Methodology Applied
Scientific EffectCapillary action: Capillary Action

Data Source

PatentUS20260047464A1Semiconductor package
Publication Date: 2026.02.12 SAMSUNG ELECTRONICS CO LTD
  • US20260047464A1 patent drawing
  • US20260047464A1 patent drawing
  • US20260047464A1 patent drawing

AI summary

A semiconductor package including a first package substrate having a first surface and a second surface, the second surface being opposite to the first surface; a first semiconductor chip on the second surface of the first package substrate; an interposer including a third surface and a fourth surface, the fourth surface being opposite to the third surface, and the third surface facing the first semiconductor chip; a second package substrate on the interposer, and a connection terminal being between the second package substrate and the interposer; and a second semiconductor chip on the second package substrate. The interposer defines a cavity that is an indentation in at least a portion of the fourth surface, and the connection terminal is in the cavity.