Interposer Cavity for Thinner 3D Package Structure
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Solution Overview
Problem
Existing semiconductor packaging techniques have limitations in achieving smaller, more efficient package structures with improved electrical performance and reduced signal noise, particularly in 3D-IC devices, due to constraints in feature size reduction and integration density.
Innovation Solution
The development of a 3D packaging process involving a package substrate with laminated insulating layers and conductive features, an interposer substrate with through-vias and a redistribution layer, and semiconductor devices bonded using conductive structures and underfill elements, allowing for thinner package structures and improved electrical connectivity through cavities and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but package size cannot be reduced further and integration density is limited
Solution Approach 1:
The patent embeds cavities within the interposer substrate, creating a nested structure where semiconductor devices are placed inside the interposer volume rather than only on its surface. This allows three-dimensional integration that reduces overall package footprint while accommodating multiple devices, effectively applying the nesting principle to achieve higher density without proportionally increasing complexity
Solution Approach 2:
The invention transitions from traditional two-dimensional surface mounting to three-dimensional integration by forming cavities that extend vertically into the interposer substrate. This dimensional change enables devices to be stacked and arranged in multiple layers, reducing the horizontal package area while utilizing the vertical dimension for increased integration density
2Productivity
If feature size is reduced to increase integration density, then more devices fit on chip area, but signal noise and RC delay increase
Solution Approach 1:
The patent divides the interposer substrate into multiple separate cavities, each housing individual semiconductor devices. This segmentation isolates the electrical signals from different devices, reducing electromagnetic interference and signal noise between adjacent devices while maintaining high integration density through efficient spatial arrangement
Solution Approach 2:
The interposer substrate with its embedded cavities acts as an intermediary structure between the package substrate and the semiconductor devices. This intermediary provides optimized electrical interconnections through through-vias and redistribution layers, reducing RC delay by shortening signal paths while enabling high-density device placement that would otherwise increase noise
3Length of stationary object
If package structure is made thinner, then smaller package size is achieved, but thermal management becomes more difficult
Solution Approach 1:
The patent creates localized thermal management zones by forming cavities that provide direct thermal pathways from heat-generating semiconductor devices to the package substrate. The cavity structures concentrate thermal conduction paths at specific locations where heat needs to be removed, rather than requiring uniform thermal management throughout the entire package volume, enabling effective heat dissipation in a thinner profile
Data Source
AI summary
A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate over the package substrate, and multiple semiconductor devices over the interposer substrate. The interposer substrate also has one or more cavities to receive or accommodate additional semiconductor devices that are not allowed to be mounted on the surface of the interposer substrate. The cavities enable a thinner overall package structure. Some semiconductor devices received in the interposer substrate cavities may also be electrically connected to the interposer substrate and/or the semiconductor devices over the interposer substrate in order to improve the electrical performance of the overall package structure.