Interposer Charge Attracting Structures for Stacked Die Protection
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Solution Overview
Problem
Stacked die assemblies face risks of damage from electrostatic discharge and charge accumulation due to the lack of effective charge protection in passive interposers, which can lead to reduced yield and reliability.
Innovation Solution
Incorporating a plurality of charge attracting structures and through-substrate vias in the interposer to provide a conductive path for charged particles, thereby protecting integrated circuit dies from surface charge discharges and ensuring proper grounding during fabrication and testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple integrated circuit dies are stacked to form a stacked die assembly, then power consumption is reduced, current leakage is reduced, performance is improved, and IC size is reduced, but the risk of charge damage to the integrated circuit dies increases
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the integrated circuit dies in the stacked die assembly. The interposer includes charge attracting structures that act as mediators to capture and dissipate charged particles before they can reach and damage the integrated circuit dies, thereby protecting the dies while enabling the stacked configuration
Solution Approach 2:
The patent converts the harmful charged particles into a beneficial effect by using charge attracting structures that deliberately attract and concentrate the charged particles in specific regions. This controlled attraction prevents the charged particles from reaching the integrated circuit dies, transforming the potential damage into a protective mechanism
2Reliability
If charge protecting structures are added to the interposer, then integrated circuit dies are protected from charge damage, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing charge attracting structures only in specific regions of the interposer where charge accumulation is most problematic. Rather than protecting the entire interposer uniformly, the charge attracting structures are strategically placed to provide protection where needed while maintaining simplicity in other areas
Solution Approach 2:
The patent segments the charge protection function into multiple discrete charge attracting structures distributed across the interposer. Each structure handles charge attraction in its local region, and the structures can be independently designed and positioned, allowing the protection function to be added without requiring a complete redesign of the entire interposer structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates the risk of damage to integrated circuit dies by attracting and dissipating charged particles, enhancing the yield and reliability of stacked die assemblies while maintaining a cost-effective manufacturing process.
Implementation Method 1
A portion of the plurality of through-substrate vias are coupled to the plurality of charge attracting structures for conduction of charged particles from the plurality of through-substrate vias to the plurality of charge attracting structures
Implementation Method 2
the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures is to protect at least one integrated circuit die to be coupled to the interposer
Data Source
Figure 1
Figure 2-1~2-3
Figure 3-1
AI summary
An apparatus relating generally to an interposer (600, 700, 800) is disclosed. In such an apparatus, the interposer (600, 700, 800) has a plurality of conductors (208, 451 -459, 603-606) and a plurality of charge attracting structures (610, 620, 710, 720, 810, 820). The plurality of charge attracting structures (610, 620, 710, 720, 810, 820) are to protect at least one integrated circuit die (202) to be coupled to the interposer (600, 700, 800) to provide a stacked die (200). The plurality of conductors (208, 451 -459, 603-606) include a plurality of through- substrate vias (208).