Interposer Chip Arrangement Dense Packaging
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Solution Overview
Problem
Current dense packaging techniques for semiconductor chips face challenges in achieving compact and efficient arrangements, particularly in reducing lateral and vertical dimensions while maintaining effective electrical connections.
Innovation Solution
The interposer-chip-arrangement involves a silicon wafer with dielectric layers and embedded metal layers, through-substrate vias for electrical connections, and a cover layer with openings for chip mounting, allowing for dense packaging and reduced dimensions through redistribution metal layers and flip-chip technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafer-to-wafer or chip-to-wafer direct bonding techniques are used for dense packaging, then chip arrangement density is improved, but manufacturing complexity increases
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the chips and the final package. The interposer provides through-substrate vias and redistribution layers that simplify the bonding process by serving as a common interface for multiple chips, thereby reducing overall manufacturing complexity while enabling dense chip arrangements
Solution Approach 2:
The packaging structure is divided into separate functional components: chips, interposer substrate, through-substrate vias, and redistribution layers. This segmentation allows each component to be manufactured and prepared independently before assembly, reducing the complexity of the overall manufacturing process while achieving high-density packaging
2Volume of moving object
If through-silicon vias and advanced wiring methods are used, then package dimensions are reduced, but manufacturing precision requirements increase
Solution Approach 1:
Through-substrate vias are formed and redistribution layers are prepared on the interposer substrate before chip mounting. This preliminary preparation of connection pathways eliminates the need for high-precision alignment during the bonding process, as the vias and layers are pre-positioned to receive chips at standard locations
Solution Approach 2:
The interposer substrate with pre-formed through-substrate vias acts as a mediator that absorbs the alignment tolerances. The redistribution layers on the interposer provide flexible routing that can accommodate variations in chip positioning, thereby reducing the precision requirements for chip-to-substrate bonding
3Reliability
If redistribution layers are implemented for electrical connections, then electrical connectivity is enhanced, but device complexity increases
Solution Approach 1:
The redistribution layers on the interposer substrate serve multiple functions: they provide electrical connections between through-substrate vias and chip contact pads, enable signal routing, and facilitate impedance matching. By consolidating these functions into a single multi-functional layer structure, the overall device complexity is managed while achieving enhanced electrical connectivity
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
The interposer-chip-arrangement comprises an interposer (1), metal layers arranged above a main surface (10), a further metal layer arranged above a further main surface (11) opposite the main surface, an electrically conductive interconnection (7) through the interposer, the interconnection connecting one of the metal layers and the further metal layer, a chip (12) arranged at the main surface or at the further main surface, the chip having a contact pad (15), which is electrically conductively connected with the interconnection, a dielectric layer (2) arranged above the main surface with the metal layers embedded in the dielectric layer, a further dielectric layer (3) arranged above the further main surface with the further metal layer embedded in the further dielectric layer, and an integrated circuit (25) in the interposer, the integrated circuit being connected with at least one of the metal layers (5).