Interposer Chip Wire Bonding Burr Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face issues such as bonding wire malfunctions due to electrically conductive burrs, signal cross-talk, alignment challenges, position drift, and increased thickness, which affect the reliability and efficiency of the semiconductor device.
Innovation Solution
The semiconductor device incorporates an interposer chip with strategically arranged electrodes and bonding wires, along with a manufacturing method that includes alignment marks and controlled adhesive strength, to prevent bonding wire contact with burrs, reduce signal cross-talk, and minimize device thickness, while ensuring stable resin sealing and wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a microcomputer chip is directly connected to a wiring substrate by bonding wire, then the device structure is simple, but the bonding wire contacts electrically conductive burrs on the chip end face causing malfunction
Solution Approach 1:
An interposer chip is introduced as an intermediary component between the microcomputer chip and the wiring substrate. The interposer chip has bonding pads arranged such that bonding wires connect the microcomputer chip to the interposer chip, and then from the interposer chip to the wiring substrate. This intermediary structure prevents bonding wires from directly contacting the end face of the microcomputer chip where conductive burrs are present, thereby eliminating the malfunction issue while maintaining a manageable device structure.
2Reliability
If an interposer chip is introduced to prevent bonding wire contact with burrs, then bonding wire reliability improves, but the device thickness increases
Solution Approach 1:
The bonding pads on the interposer chip are strategically arranged at different positions and with different spacing configurations. By optimizing the parameters of pad location, pad size, and inter-pad distance, the design achieves reliable bonding wire connections that avoid burr contact while minimizing the vertical space occupied by the interposer chip, thus controlling the overall device thickness.
3Length of stationary object
If bonding pads are arranged closely on the interposer chip to reduce thickness, then device thickness decreases, but signal cross-talk between adjacent wirings increases
Solution Approach 1:
Different regions of the interposer chip are designed with different bonding pad arrangements tailored to their specific functional requirements. Signal pads that are prone to cross-talk are positioned with adequate spacing or oriented in directions that minimize electromagnetic interference, while power and ground pads are arranged for optimal electrical performance. This localized optimization allows closely spaced pads overall while preventing cross-talk in critical signal paths.
4Stability of the object's composition
If adhesive strength between chips is increased to prevent position drift, then chip position stability improves, but the risk of chip breakage during manufacturing increases
Solution Approach 1:
Alignment marks are pre-formed on the chips before the bonding process. These marks enable precise alignment to be established before the adhesive is applied and before the chips are subjected to manufacturing stresses. By securing the correct positional relationship in advance, the design allows for optimized adhesive selection and application that provides sufficient position stability without requiring excessively high adhesive strength that would cause chip breakage during handling and manufacturing.
Data Source
AI summary
A semiconductor device in which memory chips are stacked on the surface of a wiring substrate has a microcomputer chip and an interposer chip arranged on the surface of the memory chip. The pads of the microcomputer chip and the pads of the interposer chip are arranged almost circularly and are connected by bonding wires.