Interposer Chip Assembly for Electrical Isolation in GaN Packages
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Solution Overview
Problem
Unwanted electrical coupling between semiconductor components formed on a common substrate, particularly in GaN transistors and ICs, leads to performance degradation and circuit malfunction when different body biases are applied.
Innovation Solution
Forming GaN transistors and ICs on separate semiconductor chips and using an interposer with small solder microbumps for bonding, ensuring electrical isolation and minimizing distances between chips to reduce parasitic inductances, resistances, and capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If semiconductor components are formed on a common substrate, then manufacturing complexity is reduced, but unwanted electrical coupling occurs between components
Solution Approach 1:
The patent divides the semiconductor structure into multiple separate chips, each formed on its own substrate. This segmentation eliminates the electrical coupling that would occur between components on a common substrate, as each chip is electrically isolated. The separate chips are then bonded to an interposer substrate, achieving both electrical isolation and integrated functionality.
Solution Approach 2:
The patent introduces an interposer substrate as an intermediary between the separate semiconductor chips. This interposer serves as a mediator that provides electrical connections between the isolated chips while maintaining their electrical isolation from each other. The interposer enables signal routing and power distribution without creating unwanted coupling between the separate chip components.
2Object-generated harmful factors
If separate semiconductor chips are used to provide electrical isolation, then electrical coupling is eliminated, but device complexity increases
Solution Approach 1:
The interposer substrate acts as an intermediary that simplifies the overall device architecture by providing a centralized platform for connecting multiple isolated chips. Instead of creating complex point-to-point connections between separate chips, the interposer provides a structured routing network that manages electrical connections efficiently, reducing the complexity of inter-chip interconnects.
Solution Approach 2:
The interposer substrate serves multiple functions simultaneously: it provides electrical isolation between chips, routes signals between components, distributes power to different chips, and provides mechanical support for the chip assembly. This multi-functionality consolidates several required functions into a single component, reducing overall device complexity.
3Object-affected harmful factors
If chips are placed close together to minimize parasitic effects, then parasitic inductances and resistances are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary alignment features and pre-bonded chip-on-board configurations that establish precise chip positions before final assembly. By pre-positioning chips with accurate alignment marks and using automated bonding processes with controlled placement, the system achieves close chip spacing without requiring excessive manufacturing precision in the final assembly step.
Solution Approach 2:
The interposer substrate serves as a precision reference platform that defines the spatial relationships between chips. By establishing a rigid, precisely manufactured interposer as the reference frame, the system can achieve accurate chip spacing and alignment. The interposer's predefined trace geometry and mounting structures provide the precision positioning needed to minimize parasitic effects while managing manufacturing tolerances.
Data Source
AI summary
Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.