Interposer Chip Stack Packaging for Shorter Signal Paths
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved electrical characteristics and compact size while efficiently connecting stacked semiconductor chips, which affects signal transfer speeds and reliability.
Innovation Solution
A semiconductor package design featuring an interposer substrate with an upper semiconductor chip and multiple stacked lower semiconductor chips, connected through through vias and bump patterns, and encapsulated with a molding layer to reduce electrical path lengths and enhance thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked vertically to improve integration density, then the package size is reduced, but the electrical connection complexity and signal transfer path increase
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the upper logic chip and lower memory chip stacks. The interposer substrate contains redistribution layers and through-substrate vias that simplify the electrical connection architecture, enabling compact vertical stacking while maintaining manageable connection complexity through standardized interface layers.
Solution Approach 2:
The patent transitions from planar 2D chip arrangement to 3D vertical stacking architecture. Multiple memory chip stacks are arranged vertically on the interposer substrate, with chips stacked in the thickness direction, thereby achieving higher integration density within a reduced footprint area while utilizing the third dimension for signal routing.
2Ease of manufacture
If longer electrical connection paths are used to connect stacked chips, then manufacturing flexibility increases, but signal transfer time and electrical resistance increase
Solution Approach 1:
The interposer substrate implements local quality optimization by providing different electrical path characteristics in different regions. Through-substrate vias create short vertical connection paths through the interposer thickness, while redistribution layers provide optimized horizontal routing paths, thereby minimizing overall signal transfer distance and resistance while maintaining manufacturing flexibility.
3Reliability
If multiple through vias are implemented in each chip stack to improve electrical connectivity, then connection reliability increases, but manufacturing complexity and cost increase
Solution Approach 1:
The electrical connection path is segmented into multiple functional components: bond pads on individual chips, bump electrodes for inter-chip connections, through-substrate vias in the interposer, and redistribution layers. This segmentation allows each component to be optimized independently and manufactured using specialized processes, improving overall connection reliability while managing manufacturing complexity through modular assembly.
Data Source
AI summary
A semiconductor package includes an interposer substrate; an upper semiconductor chip on a top surface of the interposer substrate, such that a bottom surface of the upper semiconductor chip faces the top surface of the interposer substrate, a chip stack on a bottom surface of the interposer substrate and including a plurality of stacked lower semiconductor chips, wherein each of the lower semiconductor chips includes a plurality of through vias therein, wherein a top surface of the chip stack faces the bottom surface of the interposer substrate, a molding layer that covers a sidewall of the chip stack, a sidewall of the interposer substrate, and a sidewall of the upper semiconductor chip, and a plurality of connection terminals disposed below a bottom surface of the chip stack opposite the top surface of the chip stack, and coupled to the through vias. The upper semiconductor chip is electrically connected through the interposer substrate to the through vias.