Interposer-Sealed Chip Stack Packaging for Flexible Testing
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Solution Overview
Problem
Existing semiconductor technologies face challenges in integrating multiple chip structures efficiently, limiting flexibility in interconnection and complicating testing and failure analysis, while also requiring protection against environmental factors.
Innovation Solution
A semiconductor package structure that includes an interposer layer with interconnection regions connecting chip stacks to a base plate, sealed by a molding layer with a protective material layer on the sidewall, allowing independent packaging and enhanced interconnection flexibility, and incorporating conductive or insulating material layers for protection and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chip structures are integrated in existing semiconductor technologies, then circuit functionality is enhanced, but interconnection flexibility is limited and testing becomes complicated
Solution Approach 1:
The patent divides the semiconductor package into separate modules: a first package structure containing a first chip stack body, and a second package structure containing a second chip stack body. These modules are interconnected through an interposer layer with connection regions, allowing independent packaging and testing of each module while maintaining flexibility in interconnection configurations.
Solution Approach 2:
The interposer layer serves as an intermediary component between the first and second package structures. It includes first connection regions that connect to the first chip stack body and second connection regions that connect to the second package structure, enabling flexible interconnection while simplifying testing through modular architecture.
2Ease of manufacture
If chip structures are packaged together in a single unit, then integration is achieved, but testing and failure analysis become difficult
Solution Approach 1:
The patent implements segmentation by creating separate first and second package structures that are interconnected but independently packaged. Each package structure can be tested and analyzed separately, reducing failure analysis difficulty while maintaining manufacturing efficiency through standardized interconnection interfaces.
3Ease of operation
If the interposer layer is exposed without protection, then interconnection access is easier, but the structure is vulnerable to environmental factors
Solution Approach 1:
The patent applies local quality by forming a protective material layer specifically on the sidewall of the interposer layer in the region where it contacts the second package structure. This localized protection preserves interconnection access functionality while protecting the vulnerable sidewall region from environmental factors.
Solution Approach 2:
The protective material layer forms a composite structure with the interposer layer, combining the electrical connection properties of the interposer material with the environmental protection properties of the protective material, achieving both interconnection access and environmental resistance.
Data Source
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AI summary
The embodiments of the present application disclose a semiconductor package structure and a manufacturing method. The semiconductor package structure includes: a first base plate provided with a first surface; a first chip stack body located on the first base plate, where the first chip stack body includes a plurality of first semiconductor chips that are successively stacked onto one another in a direction perpendicular to the first base plate, and is electrically connected to the first surface of the first base plate; an interposer layer located on the chip stack body and provided with a first interconnection surface, where the first interconnection surface is provided with a first interconnection region and a second interconnection region, and the first interconnection region is electrically connected to the first base plate; and a molding layer configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate. The first interconnection region is unsealed by the molding layer, and the second interconnection region is sealed by the molding layer. A first material layer is formed on a sidewall between the first interconnection region and a top surface of the molding layer on the second interconnection region.