Interposer Substrates With Common Redistribution Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing circuit assemblies face challenges in achieving high-density interconnects and thermal stress management between integrated circuits (ICs) and printed circuit boards (PCBs), with fragile interposers being difficult to fabricate and align, and requiring additional bridging components that increase stress on connections.
Innovation Solution
A common redistribution layer (RDL) is fabricated across multiple interposers, allowing for shorter, faster interconnects and eliminating the need for bridging dies, while interposers are manufactured from a single wafer with a common RDL, allowing for stronger heat dissipation and simplified alignment during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate interposers are used to interconnect ICs and PCBs, then thermal stress management is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
Multiple separate interposers are merged into a single integrated interposer structure that maintains the thermal stress management benefits of multiple interposers while eliminating the complexity of fabricating and aligning multiple separate components. The unified interposer is formed as one continuous substrate with integrated interconnect pathways.
Solution Approach 2:
The unified interposer is segmented into multiple functional regions that correspond to the functionality of separate interposers, allowing thermal stress management to be distributed across different zones while maintaining structural unity. This segmentation is achieved through patterned conductive layers and strategic via placements rather than physical separation.
2Quantity of substance
If bridging dies are added to interconnect interposers, then interconnect density is improved, but stress on connections increases
Solution Approach 1:
The bridging die component is extracted from the interconnection architecture and replaced with direct interconnect pathways formed within the unified interposer substrate. This eliminates the additional mechanical stress that bridging dies impose on solder connections while maintaining high interconnect density through planar routing techniques.
Solution Approach 2:
Interconnect density is achieved by utilizing the planar dimension of the unified interposer substrate rather than adding vertical stacking with bridging dies. Multiple interconnect layers are formed within the same plane, distributing stress horizontally rather than concentrating it at vertical interfaces.
3Volume of moving object
If interposers are made fragile to achieve thin profile, then package size is reduced, but manufacturing precision and alignment become more difficult
Solution Approach 1:
The interposer utilizes composite material construction combining a thin substrate base with reinforced conductive layers and via structures. This composite approach maintains the thin profile needed for compact packaging while the layered composite structure provides sufficient mechanical strength for precise fabrication and alignment operations.
Solution Approach 2:
Alignment features and reference marks are incorporated into the unified interposer during the initial fabrication process, enabling precise alignment with ICs and PCBs before final assembly. The preliminary inclusion of alignment structures eliminates the need for post-fabrication alignment adjustments that would be particularly difficult with fragile thin interposers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances interconnect density, reduces thermal stress, and improves the mechanical strength of the circuit assembly by providing a more efficient and robust interconnection method between ICs and PCBs, while also simplifying the fabrication process.
Implementation Method 1
an interposer may absorb some of the thermal expansion stresses resulting from differences in the coefficients of thermal expansion (CTE) between the ICs, the PCB, and other parts of a circuit assembly
Implementation Method 2
A common redistribution layer (RDL) is fabricated across multiple interposers, allowing for shorter, faster interconnects
Implementation Method 3
interposers are manufactured from a single wafer with a common RDL, allowing for stronger heat dissipation
Data Source
AI summary
A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.