Interposer Core Filled Vias for Ultra-Thin PoP Solder Bridging

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Solution Overview

Problem

Current semiconductor microelectronic device packaging technologies face challenges in achieving efficient vertical communication and tight pitch between electrical channels, often resulting in solder bridging and limited pitch options.

Innovation Solution

The use of patterned interposer cores with filled vias, which provide a communicative channel between chip bottom and top packages, avoiding solder bridging and allowing for tighter pitch configurations by incorporating electrically conductive materials and structured plating processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional solder bump connections are used for inter-package connections, then the packaging process is simpler, but solder bridging occurs and pitch options are limited

Engineering Contradiction:

Improveconnection reliabilityVSAvoidsolder bridging

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an interposer core as an intermediary component between the bottom and top packages. This interposer core with filled vias acts as a mediator that enables electrical connection without direct solder bump contact between packages, thereby eliminating solder bridging while maintaining connection reliability

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the traditional mechanical solder bump connection system with an electrical field-based connection system through filled vias. The vias are filled with conductive material to create electrical pathways, substituting the mechanical solder joint approach with a more reliable electrical conduction method

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If traditional packaging structures are used, then the manufacturing process is simpler, but vertical communication efficiency is reduced

Engineering Contradiction:

Improvevertical communication efficiencyVSAvoidpackage structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from traditional lateral/planar communication layouts to vertical three-dimensional communication pathways. By stacking packages vertically and using through-vias in the interposer core, the patent enables efficient vertical signal transmission, improving communication efficiency by utilizing the Z-dimension

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the interposer core into multiple functional layers with segmented vias at different levels. The interposer core is segmented into a bottom portion, middle portion, and top portion, each with specific via configurations that enable staged electrical connections and improved signal routing efficiency

Inventive Principle:

Principle #1Segmentation

3Quantity of substance

If standard pitch configurations are used, then manufacturing is easier, but packaging density is limited

Engineering Contradiction:

Improvepackaging densityVSAvoidpitch configuration precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent changes the pitch parameter configurations by implementing non-uniform pitch distributions. Different pitch values are used in different regions of the interposer core, allowing optimization of packaging density in critical areas while maintaining manufacturability. The pitch parameters are varied to accommodate different via sizes and spacing requirements

Inventive Principle:

Principle #35Parameter changes

4Ease of manufacture

If larger via pitch is used, then manufacturing is easier, but electrical channel density is reduced

Engineering Contradiction:

Improvevia fabrication easeVSAvoidelectrical channel density

Core Design Contradiction:

Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent applies local quality by using different via pitch values in different regions of the interposer core. Areas requiring high electrical channel density use smaller pitches, while areas where ease of manufacture is prioritized use larger pitches. This localized optimization allows the system to achieve high overall density without compromising manufacturability throughout the entire structure

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables efficient vertical communication and tighter pitch options between electrical channels, reducing the risk of solder bridging and enhancing packaging density, as demonstrated by various pitch and height combinations in the described embodiments.

Implementation Method 1

an electroless plating process is performed to form an electroless-plated via

Methodology Applied

Scientific EffectElectroless plating: Electroplating

Implementation Method 2

an electroplating process is performed to fill the via with copper material

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS8987896B2High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same

Publication Date: 2015.03.24 INTEL CORP

AI summary

An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.