Interposer CTE Matching for Semiconductor Package Warpage
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Solution Overview
Problem
Conventional Package-on-Package (PoP) structures face issues such as warpage due to mismatched coefficients of thermal expansion (CTEs) between laminated substrates and dies, affecting robustness and incurring additional costs.
Innovation Solution
The use of an interposer with through interposer vias, where the interposer material has a CTE similar to that of the die, facilitating electrical coupling and reducing thermal expansion mismatches, and featuring conductive contacts coupled to the vias for improved structural integrity and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a laminated substrate is used in conventional PoP structures, then electrical coupling and structural support are provided, but warpage occurs due to CTE mismatch between substrate and die
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the die and the laminated substrate. This interposer has a CTE that matches the die, serving as a thermal expansion mediator that eliminates warpage while maintaining electrical coupling through through-substrate vias.
Solution Approach 2:
The patent changes the CTE parameter of the intermediate layer by selecting interposer material with CTE similar to the die rather than the substrate. This parameter change resolves the thermal expansion mismatch that causes warpage in conventional structures.
2Reliability
If an additional laminated substrate is used for electrical coupling, then connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The interposer serves as a cost-effective intermediary that provides necessary electrical connectivity through integrated through-substrate vias, eliminating the need for additional expensive laminated substrates while maintaining reliable electrical coupling between die and package.
3Volume of moving object
If conventional PoP stacking is used, then compact packaging is achieved, but CTE mismatch causes warpage and reliability issues
Solution Approach 1:
The interposer acts as a mediator in the stacked package structure, enabling compact PoP configuration while resolving CTE mismatch issues. The through-substrate vias provide both mechanical support and electrical connectivity without compromising package robustness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness of semiconductor assemblies by minimizing warpage and reducing costs associated with additional substrates, while maintaining electrical connectivity and thermal expansion compatibility.
Implementation Method 1
The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die
Implementation Method 2
The through interposer vias facilitate electrical coupling between the interposer contact pads on the first and second surfaces of the interposer
Data Source
AI summary
A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.