Interposer Dam Structure for Bump Bridging Prevention

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Solution Overview

Problem

Current integrated circuit manufacturing and packaging face challenges in efficiently utilizing through vias and interposers to meet increasing demand for compact portable devices, particularly in managing board size and preventing bump bridging and warpage during reflow processes.

Innovation Solution

A die-on-interposer assembly with a dam structure is developed, where dam structures are formed on the backside of the interposer chip to control the gap between the assembly and the substrate, using polymer materials with high adhesive properties, and are designed to prevent bump bridging and warpage by aligning with corner edges of the interposer chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If through vias are used to enable wafer level processing and increase memory density, then board area utilization is improved, but bump bridging and warpage occur during reflow processes

Engineering Contradiction:
Improveboard areaVSAvoidbump bridging and warpage
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces an interposer as an intermediary component between the die and substrate. The interposer provides through vias for electrical coupling while its structured backside with dam structures prevents direct contact between bumps from adjacent dies, thereby preventing bump bridging and reducing warpage during reflow processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the assembly into distinct components: die, interposer, and substrate. The interposer is further segmented with dam structures that create isolated regions. This segmentation allows through via connections for high density while the dam structures physically separate bumps to prevent bridging

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If dam structures are formed on the backside of the interposer chip to control the gap, then gap control and warpage prevention are improved, but manufacturing complexity increases

Engineering Contradiction:
Improvegap controlVSAvoidmanufacturing process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dam structures are formed on the backside of the interposer chip before die attachment. This preliminary action establishes the gap control features in advance, ensuring proper spacing and preventing warpage before the assembly process begins, thereby simplifying subsequent manufacturing steps

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dam structures effectively manage the gap between the interposer chip and the substrate, preventing bump bridging and warpage, and improve throughput and stability in packaging processes, addressing the limitations of existing technologies in compact device manufacturing.

Implementation Method 1

using polymer materials with high adhesive properties

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS11488882B2Die-on-interposer assembly with dam structure and method of manufacturing the same
Publication Date: 2022.11.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11488882B2 patent drawing
  • US11488882B2 patent drawing
  • US11488882B2 patent drawing

AI summary

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.