Interposer Die Layout to Reduce Cracking in Semiconductor Packages

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Solution Overview

Problem

Advanced semiconductor packaging processes face challenges in structural strength and integrity, particularly due to warpage and cracking caused by thermal expansion mismatch during the heating process, which can lead to unreliable package structures and reduced yield.

Innovation Solution

The arrangement of dies relative to the crystallographic orientation of the underlying crystalline semiconductor wafer interposer is optimized, with the gap between dies oriented non-parallel to the crystallographic orientation, minimizing stress transfer and reducing the likelihood of cracking, and the use of specific bonding and encapsulation processes to enhance interposer strength.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional die arrangement with gaps parallel to crystallographic orientation is used, then manufacturing simplicity is maintained, but interposer cracking occurs due to stress concentration during thermal expansion

Engineering Contradiction:

Improveinterposer structural integrityVSAvoiddie arrangement complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by deliberately orienting the gap between adjacent dies at an angle that is not parallel to the crystallographic orientation of the interposer. This asymmetric arrangement prevents stress concentration along the crystallographic directions during thermal expansion, thereby reducing interposer cracking while maintaining manufacturing feasibility

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The patent changes the geometric parameter of die arrangement by specifying that gaps between dies should be oriented at non-parallel angles relative to crystallographic orientation. This parameter modification optimizes stress distribution during thermal cycling, improving interposer reliability without significantly complicating the manufacturing process

Inventive Principle:

Principle #35Parameter changes

2Reliability

If bonding process is performed to integrate multi-chips onto interposer, then package functionality is achieved, but warpage and cracking occur due to thermal expansion mismatch

Engineering Contradiction:

Improvepackage structural reliabilityVSAvoidthermal expansion mismatch effects

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by optimizing the die arrangement specifically at the gap regions between adjacent dies. By orienting these gaps at non-parallel angles to crystallographic orientation, the patent locally reduces stress concentration points where thermal expansion mismatch would otherwise cause warpage and cracking during bonding and thermal cycling

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent converts the potentially harmful effect of thermal expansion mismatch into a beneficial outcome by strategically arranging die gaps. The non-parallel orientation transforms what would be stress concentration zones into stress-distributing features, reducing warpage and cracking while maintaining the necessary bonding process for package functionality

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces interposer cracking and enhances the structural reliability and yield of semiconductor packages by improving the strength of the interposer, especially at gaps prone to warpage, resulting in more robust and reliable package structures.

Implementation Method 1

warpage and cracking caused by thermal expansion mismatch during the heating process

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11742276B2Semiconductor package and manufacturing process thereof

Publication Date: 2023.08.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.