Interposer-Based Die Stack With Fine-Pitch Through Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of achieving tight pitch through silicon vias (TSVs) and through glass vias (TGVs) in microelectronic structures is exacerbated by the need for thin top dies, which are prone to cracking due to thermal expansion mismatch and require complex processing with temporary carriers, leading to inefficiencies and waste of transistor area.
Innovation Solution
A face to back process flow that utilizes a passive interposer substrate with hybrid bonding and thinner through vias, eliminating the need for temporary carriers and reducing die cracking risks, while allowing for finer pitches and smaller via diameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tight pitch through vias are implemented to achieve die to die coupling, then electrical and mechanical coupling between dies is improved, but the top die thickness must be reduced to less than 50 μm which causes mechanical strength deterioration and cracking susceptibility
Solution Approach 1:
A carrier substrate is introduced as an intermediary component to support the top die during processing and bonding. The carrier substrate provides mechanical strength and stability, allowing the top die to maintain sufficient thickness while enabling tight pitch through via formation. The carrier acts as a temporary support structure that is removed after bonding is complete.
Solution Approach 2:
The top die is thinned to the required thickness and through vias are formed in advance on the carrier substrate before the actual die to die bonding process. This preliminary preparation allows precise control of through via dimensions and pitch while the die is still supported by the carrier, avoiding mechanical failure during subsequent processing.
2Manufacturing precision
If the top die thickness is reduced to accommodate smaller through vias and tighter pitches, then through via pitch and size are improved, but thermal expansion mismatch causes die cracking
Solution Approach 1:
The carrier substrate serves as a thermal buffer and mechanical support during the bonding process. It absorbs and distributes thermal stresses that arise from thermal expansion mismatch, preventing these stresses from concentrating in the thin top die and causing cracks. The carrier protects the die throughout the high-temperature bonding process.
3Manufacturing precision
If complex processing with glue carriers is used to achieve tight pitch through vias, then through via pitch is improved, but process complexity and manufacturing steps increase
Solution Approach 1:
The carrier substrate is designed as a temporary, disposable support structure that is removed after serving its purpose. This allows the use of simple, cost-effective carrier materials that can be easily attached and detached, reducing the overall complexity compared to permanent support structures. The carrier is discarded after enabling the tight pitch through via formation.
4Ease of manufacture
If conventional through via methods are used without carrier support, then process simplicity is maintained, but through via pitch must be increased to at least 20 μm
Solution Approach 1:
The carrier substrate enables tight pitch through via formation by providing the necessary mechanical support and stability during processing. It acts as a platform that allows precise positioning and formation of small-diameter through vias at close spacing, which would be impossible to achieve with direct die processing alone.
Data Source
AI summary
A microelectronic component and a method of forming same. The microelectronic component includes: a first substrate having first through vias therein, the first substrate including silicon or glass; a first layer on a front surface of the first substrate and including one or more first dies coupled to the first through vias; a second substrate on a front surface of first layer and having second through vias therein and including silicon or glass; a second layer on a front surface of the second substrate, the first layer between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias; and electrically conductive structures on a back surface of the first substrate coupled to the first through vias.


