Interposer Chip With Integrated Diode for Wire-Bond Monitoring
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Solution Overview
Problem
Conventional semiconductor stack packages face yield reduction and increased testing costs due to undetected wire-bonding defects between interposer chips and semiconductor chips, as existing interposer chips lack the ability to monitor wire-bonding success, leading to misidentification of defective chips.
Innovation Solution
Incorporating an interposer chip with a circuit element, such as a diode or capacitor, connected to a bonding pad that allows for wire-bond monitoring by applying current and measuring voltage or current to detect proper bonding, enabling detection of non-stick defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional interposer chip with only I/O bonding pads is used, then the structure is simple and manufacturing is easy, but wire-bonding defects cannot be detected leading to decreased yield
Solution Approach 1:
The patent incorporates circuit elements (diodes or capacitors) into the interposer chip before wire-bonding occurs. These elements are pre-positioned and connected to bonding pads, enabling subsequent detection of wire-bonding quality through electrical measurements. This preliminary preparation allows defect detection capability to be built into the structure without adding complex external testing equipment.
Solution Approach 2:
The circuit elements (diodes or capacitors) serve as intermediary components between the wire-bond and the measurement system. When a wire is bonded to a bonding pad connected to a circuit element, the electrical properties of that element (forward voltage for diodes, impedance for capacitors) provide a measurable signal that indicates bonding quality. This intermediary mechanism translates physical bonding quality into detectable electrical parameters.
2Measurement precision
If wire-bonding is performed without monitoring capability, then the manufacturing process is faster and simpler, but defective wire-bonds are not detected causing misidentification of semiconductor chips as defective
Solution Approach 1:
The patent implements a feedback mechanism where electrical measurements are taken immediately after wire-bonding to verify bonding quality. By measuring the electrical properties of circuit elements connected to bonding pads, the system provides real-time feedback on whether the wire-bond was successful. This allows defective bonds to be identified and corrected before proceeding to subsequent manufacturing steps, preventing misidentification of semiconductor chips.
Solution Approach 2:
The interposer chip with integrated circuit elements performs self-verification of wire-bonding quality. The electrical measurements are conducted using the chip's own built-in circuit elements rather than requiring external complex testing equipment. This self-service capability enables quality verification to be performed as part of the manufacturing process itself, minimizing additional time and complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for accurate detection of wire-bonding defects, reducing the misidentification of semiconductor chips as defective and decreasing the burden of subsequent testing, thereby increasing yield and reducing costs.
Implementation Method 1
the circuit element may be a capacitor
Data Source
AI summary
A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.