Interposer Substrate Layout for Direct Bump-to-Pad Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving stable electrical connections and efficient manufacturing processes, particularly due to the complexity and thickness of interposer substrates that include silicon substrates and through electrodes.
Innovation Solution
The semiconductor package design includes an interposer substrate without a silicon substrate or through electrodes, utilizing a redistribution structure with plating seed layers on redistribution layers and vias, allowing direct contact between connection bumps and lower pads, and using simplified manufacturing methods to enhance adhesion and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer substrate with silicon substrate and through electrodes is used, then electrical connection stability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the silicon substrate and through electrodes from the interposer substrate, extracting only the essential redistribution function. The interposer is reduced to a simplified structure with insulating layer, pads, and surface redistribution traces, eliminating unnecessary complexity while maintaining electrical connection stability through direct bump-to-pad contact.
Solution Approach 2:
The patent segments the interposer substrate into distinct functional layers: insulating layer, pads (upper and lower), and redistribution traces on the surface. This segmentation allows each component to perform its specific function efficiently, with the lower pad directly contacting connection bumps and the redistribution trace routing signals to the upper pad, simplifying the overall structure.
2Reliability
If an interposer substrate with through electrodes is used, then electrical connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the through electrodes from the interposer substrate structure. Instead of forming complex through-electrode pathways, the design uses surface redistribution traces that follow the contour of the insulating layer, dramatically simplifying the manufacturing process while maintaining reliable electrical connections through direct bump-to-pad contact.
Solution Approach 2:
Instead of creating through-electrode connections that penetrate the substrate, the patent inverts the approach by using surface-level redistribution traces that route connections along the outer surface of the insulating layer. This inversion simplifies manufacturing by eliminating the need for complex via formation and through-substrate plating processes.
3Productivity
If connection bumps directly contact lower pads, then manufacturing efficiency is improved, but adhesion stability may worsen
Solution Approach 1:
The patent applies preliminary action by forming a plating seed layer on the lower pad surface before the direct contact with connection bumps is established. This seed layer is prepared in advance during the interposer fabrication process, ensuring that when connection bumps are subsequently attached, they have immediate adhesion to a pre-prepared metallurgical surface, maintaining both manufacturing efficiency and adhesion stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves adhesion between connection bumps and pads, reduces manufacturing complexity and cost, and enhances the overall reliability of the semiconductor package.
Implementation Method 1
each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and the lower pad directly contacts the plating seed layer
Data Source
AI summary
A semiconductor package includes an interposer substrate on a package substrate. The interposer substrate includes an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating the insulating layer between the upper surface and the lower surface to connect the upper pad and the lower pad. A semiconductor chip is disposed above the interposer substrate and connected to the upper pad, and a connection bump directly contacts a lower surface of the lower pad. The redistribution structure includes redistribution layers and redistribution vias connected to the redistribution layers, wherein each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and the lower pad directly contacts the plating seed layer.