Interposer Direct Vias and Spiral Routing for High-Frequency Integrity

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing resistance and voltage drop at high frequencies due to the limitations of traditional vias and routing structures in integrated circuit packages, which affect electrical performance and signal integrity.

Innovation Solution

The implementation of direct vias through multiple redistribution layers of interposers and the formation of spiral routing stacks in interconnect structures provides more direct electrical couplings and reduces resistance, while the spiral routing stacks enhance signal and power integrity by functioning as inductors to mitigate radio interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional vias and routing structures are used in integrated circuit packages, then the structure is simpler and easier to manufacture, but resistance and voltage drop increase at high frequencies, degrading electrical performance and signal integrity

Engineering Contradiction:
Improvesignal integrityVSAvoidinterconnect structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from planar routing to three-dimensional vertical routing by implementing through-silicon vias (TSVs) that penetrate the substrate depth-wise. This dimensional change enables direct vertical electrical connections between stacked dies, reducing current path length and resistance while maintaining signal integrity at high frequencies without requiring complex lateral routing structures

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested interconnect structures where multiple routing layers and via structures are integrated within the substrate thickness. The TSVs are nested within the silicon substrate, and additional routing layers are nested around them, creating a compact three-dimensional interconnect architecture that reduces overall package size while improving electrical performance

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If more routing layers and redistribution structures are added to improve electrical connections, then resistance and voltage drop are reduced, but the manufacturing process becomes more complex and costly

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent performs preliminary actions by forming the TSVs and routing structures within the substrate before die attachment. The interconnect structures are pre-integrated into the substrate during substrate fabrication, allowing subsequent die stacking to proceed with simpler alignment and attachment processes, thereby reducing overall manufacturing complexity despite the advanced interconnect architecture

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges multiple functions into the substrate structure itself. The substrate simultaneously serves as the mechanical support platform, the electrical interconnect medium through TSVs, and the routing architecture. This consolidation eliminates the need for separate complex routing boards and reduces the number of discrete manufacturing steps required

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If conventional via structures are used, then the manufacturing process is simpler, but resistance and voltage drop increase at high frequencies, affecting electrical performance

Engineering Contradiction:
Improveelectrical performanceVSAvoidvoltage drop
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements vertical TSV routing that creates direct through-substrate electrical pathways, dramatically shortening the current transmission distance compared to conventional lateral routing. This dimensional change reduces both resistance and inductance, minimizing voltage drop and energy loss at high frequencies while improving overall electrical performance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite interconnect structures combining copper or other low-resistance conductive materials for the TSV fills with carefully engineered dielectric materials for the surrounding insulation. This composite approach optimizes both electrical performance (low resistance) and manufacturing considerations (material compatibility, processing temperatures)

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases electrical performance by reducing resistance and voltage drop, and improves signal and power integrity by enabling efficient high-frequency operations through direct vias and inductive functions in the interconnect structures.

Implementation Method 1

the spiral routing stacks enhance signal and power integrity by functioning as inductors to mitigate radio interference

Methodology Applied
Scientific EffectInductor: Inductor

Data Source

PatentUS20240079356A1Integrated Circuit Packages and Methods of Forming the Same
Publication Date: 2024.03.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240079356A1 patent drawing
  • US20240079356A1 patent drawing
  • US20240079356A1 patent drawing

AI summary

An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.