Interposer Edge Metal Layout for Thermal Crack Control

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Solution Overview

Problem

The complexity of system in package (SIP) designs and fabrication can lead to design and reliability issues due to the intricacy of connecting semiconductor chips, which affects the overall performance and reliability of semiconductor devices.

Innovation Solution

A semiconductor device design that incorporates an interposer with a base substrate, a circuit layer including an insulating member and a metal structure, where the metal structure is electrically isolated from the wiring structure and disposed in an edge region to manage thermal expansion and prevent crack generation, enhancing the reliability and manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an interposer with through silicon vias (TSV) is used to form fine wirings for connecting semiconductor chips, then the connectivity and integration density are improved, but the design and fabrication complexity increases leading to errors and reliability issues

Engineering Contradiction:
Improveintegration densityVSAvoiddesign and fabrication complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The interposer is divided into distinct functional regions: a first region containing the wiring structure for chip connections and a second region containing the metal structure for stress management. This segmentation allows each region to be optimized independently, reducing design complexity while maintaining high integration density in the wiring region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the interposer are assigned different material properties and structural characteristics. The first region has high-density wiring structures for connectivity, while the second region has metal structures with specific mechanical properties for stress control. This local differentiation reduces fabrication complexity by allowing region-specific process optimization.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the interposer structure is simplified to reduce design complexity, then manufacturing ease is improved, but the ability to manage thermal expansion and prevent cracks is reduced

Engineering Contradiction:
Improvemanufacturing easeVSAvoidcrack prevention capability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent modifies the physical and chemical parameters of the interposer by introducing metal structures with specific coefficients of thermal expansion in the second region. These parameter changes enable the interposer to accommodate thermal expansion differences between chips and substrate, preventing cracks while maintaining a manufacturable structure using standard semiconductor fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The interposer combines different materials in distinct regions: conductive materials for wiring in the first region and metal structures (such as tungsten or copper) in the second region. This composite approach provides both the electrical connectivity needed for manufacturing and the mechanical properties required for reliability, without significantly complicating the fabrication process.

Inventive Principle:
Principle #40Composite materials

3Reliability

If metal structures are added to manage thermal expansion, then reliability is improved, but the device complexity and manufacturing process difficulty increase

Engineering Contradiction:
Improvethermal expansion managementVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stress management function is extracted from the wiring structure and placed in a separate second region of the interposer. This allows the wiring structure in the first region to remain simple and focused on connectivity, while the metal structures in the second region handle thermal expansion. This separation reduces overall structural complexity by assigning specific functions to specific regions.

Inventive Principle:
Principle #2Taking out (Extraction)

4Reliability

If region-specific structures are implemented in the circuit layer, then stress distribution is improved, but the fabrication process complexity increases

Engineering Contradiction:
Improvestress distributionVSAvoidfabrication process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The circuit layer is segmented into a first region with wiring structures and a second region with metal structures. This segmentation enables stress distribution optimization in the second region while keeping the wiring region fabrication processes standard and simple. The region-specific structures are implemented using conventional photolithography and deposition techniques, maintaining fabrication ease.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design improves the reliability and manufacturing yield of semiconductor devices by managing thermal expansion and reducing the risk of crack generation, thereby enhancing the overall performance and efficiency of SIPs.

Implementation Method 1

the metal structure is electrically isolated from the wiring structure and disposed in an edge region to manage thermal expansion and prevent crack generation

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS12080691B2Semiconductor devices
Publication Date: 2024.09.03 SAMSUNG ELECTRONICS CO LTD
  • US12080691B2 patent drawing
  • US12080691B2 patent drawing
  • US12080691B2 patent drawing

AI summary

A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.