Interposer Edge Probe Signal Conditioning
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Solution Overview
Problem
Existing interposers used to access signals from components like ball grid arrays are often large and introduce parasitics due to long complex traces, making it difficult to characterize individual signals without altering their character.
Innovation Solution
A low-profile interposer with short traces and signal conditioning, featuring a substrate with arrays of contacts on the top and bottom surfaces, and edge contacts that provide electrical connections between corresponding contacts on an integrated circuit package and a board under test, minimizing signal alteration and parasitic introduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional large socket type interposers with long complex traces are used, then signal access from outside component footprint is achieved, but parasitics are introduced into the signal
Solution Approach 1:
The patent transitions from traditional planar interposer designs to a three-dimensional stacked configuration. Multiple interposer layers are vertically stacked with signal paths extending through multiple levels, utilizing the Z-dimension to reduce horizontal trace lengths and minimize parasitic effects while maintaining signal accessibility from external interfaces.
Solution Approach 2:
The patent implements nested interposer structures where smaller interposer assemblies are integrated within larger package footprints. Multiple functional layers are nested vertically, with each layer containing optimized signal paths that connect through vias and through-holes, creating a compact nested architecture that reduces overall parasitic inductance and capacitance.
2Reliability
If interposer footprint is reduced to minimize parasitics, then signal integrity is improved, but access to densely packed circuits becomes more difficult
Solution Approach 1:
The patent divides the interposer functionality into multiple independent layers, each optimized for specific signal routing tasks. This segmentation allows each layer to be designed with minimal trace lengths for its specific function, improving signal integrity while the cumulative effect of multiple layers provides comprehensive access to densely packed circuit elements through the vertical dimension.
Solution Approach 2:
By utilizing vertical stacking, the patent enables access to signals in densely packed circuits without increasing the horizontal footprint. Test probes can access signals from multiple layers through vertical approaches, and the stacked architecture allows signal paths to route through the Z-dimension, bypassing the limitations of planar space constraints in dense packaging.
Data Source
AI summary
An interposer comprising an array of top contacts on the top surface configured to interface with an integrated circuit package, a corresponding array of bottom contacts on the bottom surface configured to interface with a component beneath the interposer, through connections between corresponding top and bottom contacts and a plurality of signal probe points on the edge surface. The interposer may include an electrical pathway connecting a first through connection to a first signal probe point. The electrical pathway may contact the first through connection at a first intersection. A resistor may be disposed along the electrical pathway, between the first intersection and the first signal probe point. The electrical pathway from the first intersection to the resistor may be an unconditioned signal pathway. The electrical pathway from the resistor to the first signal contact may be a conditioned signal pathway. The unconditioned signal pathway may have a length of not greater than 0.20 inch.