Interposer Passivation Embossing to Resist Underfill Delamination
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Solution Overview
Problem
Semiconductor packages face reliability issues due to cracking in the underfill resin, which leads to interfacial delamination between the interposer substrate and the underfill resin, affecting connection reliability during thermal cycles.
Innovation Solution
An embossed pattern is introduced into the passivation layer on the interposer substrate, which reduces or prevents cracking propagation and enhances the contact area with the underfill resin, thereby improving connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flat passivation layer is used on the interposer substrate, then the manufacturing process is simple, but cracking propagates easily causing interfacial delamination between the interposer substrate and underfill resin
Solution Approach 1:
The passivation layer is transformed from a flat surface to a curved surface with embossed patterns. The embossed patterns create convex and concave regions that increase the contact area with the underfill resin, preventing cracking propagation and interfacial delamination while maintaining manufacturing feasibility through standard embossing processes
2Reliability
If the passivation layer contact area with underfill resin is increased, then cracking propagation is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The embossed patterns are strategically positioned in specific regions where cracking is most likely to occur, such as near the edges of the interposer substrate and around high-stress areas. This localized approach increases contact area where needed without requiring high precision across the entire passivation layer, reducing overall manufacturing complexity
Data Source
AI summary
A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.