Interposer Package Encapsulant Layout for Warpage and Solder Bridging

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Solution Overview

Problem

The increasing complexity of IC manufacturing processes due to reduced feature sizes in semiconductor devices necessitates advanced packaging techniques to address warpage and solder joint issues in semiconductor packages.

Innovation Solution

A novel semiconductor package structure and manufacturing method involving an interposer substrate with conductive terminals, underfill, and insulating encapsulant, which includes a molding process to encapsulate semiconductor dies and pillars, followed by planarization and patterning to facilitate precise die bonding and reduce warpage and solder joint bridging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If IC dimensions are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing process complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The patent segments the manufacturing process into distinct stages: forming the insulating encapsulant with recesses, bonding semiconductor dies to the encapsulant, and subsequent packaging steps. This segmentation allows each stage to be optimized independently, managing the complexity introduced by reduced IC dimensions while maintaining high integration density.

Inventive Principle:
Principle #1Segmentation

2Reliability

If advanced packaging techniques are used to address warpage and solder joint issues, then package reliability improves, but manufacturing complexity increases

Engineering Contradiction:
Improvepackage reliabilityVSAvoidpackaging process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming recesses in the insulating encapsulant before bonding the semiconductor dies. These pre-formed recesses accommodate solder joints and accommodate thermal expansion differences, preventing warpage and solder joint bridging before they occur during the bonding and reflow processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The insulating encapsulant acts as an intermediary between the semiconductor dies and the package substrate. It provides mechanical support, electrical insulation, and thermal management, mediating the stresses and preventing direct contact between conflicting components that would cause warpage and solder joint issues.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If insulating encapsulant is formed over conductive pillars, then electrical insulation is provided, but solder joint bridging may occur

Engineering Contradiction:
Improveelectrical insulationVSAvoidsolder joint bridging
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by forming recesses in the insulating encapsulant at specific locations where conductive pillars are present. The encapsulant maintains its insulating properties in most areas while creating localized openings that prevent solder joint bridging. This allows the encapsulant to provide electrical insulation where needed while preventing harmful solder joint contact in critical areas.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250233111A1Semiconductor package and manufacturing method of the same
Publication Date: 2025.07.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250233111A1 patent drawing
  • US20250233111A1 patent drawing
  • US20250233111A1 patent drawing

AI summary

A package structure and manufacturing methods thereof are described. The package structure includes an interposer substrate, a first semiconductor die, a second semiconductor die, an underfill, and an insulating encapsulant. The first and second semiconductor dies are disposed on the interposer substrate. The underfill is disposed between the first semiconductor die and the interposer substrate. The insulating encapsulant is disposed on the interposer substrate. The insulating encapsulant includes a first portion and a second portion. The first portion laterally encapsulates the first semiconductor die and the second semiconductor die. The second portion is disposed between the second semiconductor die and the interposer substrate.