Interposer Fabricating Process Eliminates TSVs and Adhesives
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Solution Overview
Problem
Current interposer packaging processes using through silicon vias (TSVs) and adhesives are complex and prone to defects, reducing the reliability of semiconductor devices due to the need for intricate processes.
Innovation Solution
An interposer fabricating process that eliminates TSVs and adhesive use by stacking a substrate, oxide, and dielectric layers with metal structures and barrier layers, allowing for interconnects within the dielectric layer without protrusion through the silicon, enabling direct metal structure exposure for connection without adhesives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) and adhesive are used for interconnections in interposers, then routing density and electrical performance are improved, but process complexity increases and defects occur
Solution Approach 1:
The patent extracts and eliminates the TSV structure and adhesive layer from the interposer system. Instead of using through-silicon vias that penetrate the substrate, the invention uses surface-level metal pads and interconnect structures that remain on or near the surface of the interposer substrate, thereby removing the complex drilling, plating, and filling processes associated with TSVs while maintaining electrical connectivity.
Solution Approach 2:
The patent inverts the conventional approach by not creating holes through the substrate (TSVs) but rather forming metal interconnect structures on the surface. Instead of going through the substrate vertically, the electrical connections are established through surface-mounted metal pads and traces, fundamentally reversing the routing strategy from vertical through-substrate connections to horizontal surface-level connections.
2Reliability
If through silicon vias (TSVs) and adhesive are used for interconnections in interposers, then routing density is improved, but manufacturing defects increase
Solution Approach 1:
The patent removes the TSV and adhesive components from the manufacturing process, thereby eliminating the sources of defects associated with deep via drilling, plating uniformity, and adhesive bonding. The surface-level metal interconnect structures require simpler fabrication processes that are more controllable and less prone to manufacturing variations.
3Strength
If adhesive is used for physically connecting components to interposer, then mechanical bonding is achieved, but process complexity and reliability issues arise
Solution Approach 1:
The patent extracts the adhesive layer from the connection system and replaces it with direct metal-to-metal bonding between the interposer surface pads and the component bonding pads. This eliminates the adhesive application, curing, and alignment processes while providing robust mechanical and electrical connection through the metal interconnect structures.
Solution Approach 2:
The patent uses metal pads and interconnect structures as intermediaries between the interposer substrate and the attached components. These metal structures serve dual functions as both electrical conductors and mechanical bonding interfaces, eliminating the need for separate adhesive layers while maintaining strong mechanical attachment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the packaging process, reduces defects, and enhances the reliability of semiconductor devices by eliminating the need for complex adhesive and TSV-related issues, while maintaining high routing density and electrical performance.
Implementation Method 1
The substrate and the oxide layer are removed by a removing selectivity between the oxide layer and the stop layer until the stop layer and the barrier layer are exposed
Data Source
AI summary
An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.