Interposer Package Layout for Fine-Pitch Multi-Chip Bonding
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Solution Overview
Problem
The challenge in semiconductor packaging is forming fine circuits that match the fine bump pitch of semiconductor chips, particularly in system-in-package structures with multiple chips, while ensuring product reliability.
Innovation Solution
A semiconductor package design featuring a base substrate with an interposer package and multiple semiconductor chips, utilizing a redistribution structure with insulating and redistribution layers, bridge chips, and connection structures, along with a method of fabricating this structure through layer formation, resist pattern removal, and planarization processes to create precise contact plugs and bonding structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fine bump pitch of semiconductor chip is used, then the circuit density and performance are improved, but the manufacturing precision and alignment difficulty worsen
Solution Approach 1:
An interposer package is introduced as an intermediary component between the base substrate and semiconductor chips. The interposer includes a redistribution structure with multiple insulating layers and conductive layers that enable fine pitch bump connections. This mediator absorbs the alignment complexity, allowing chips with fine bump pitch to be connected without requiring the entire packaging process to achieve ultra-fine alignment precision.
Solution Approach 2:
The packaging structure is divided into multiple segments: base substrate, interposer package with redistribution structure, and semiconductor chips. The redistribution structure itself is segmented into multiple layers (first insulating layer, first redistribution layer, second insulating layer, second redistribution layer). This segmentation allows each layer to be formed and aligned independently, making fine pitch implementation feasible through cumulative precision rather than single-step precision.
2Adaptability or versatility
If multiple semiconductor chips are embedded in one package, then the system functionality and integration are improved, but the device complexity and fabrication difficulty worsen
Solution Approach 1:
The interposer package serves multiple functions: it provides mechanical support for multiple chips, enables electrical redistribution and interconnection between chips, facilitates heat dissipation pathways, and simplifies the overall packaging process. This multi-functional design allows multiple semiconductor chips to be integrated in one package without proportionally increasing fabrication complexity.
Solution Approach 2:
The redistribution structure is formed on the interposer package before the semiconductor chips are mounted. This preliminary formation of conductive pathways and insulating layers prepares the interposer to receive and connect multiple chips in subsequent steps, reducing the complexity of on-chip interconnections and enabling modular assembly.
3Measurement precision
If a redistribution structure with multiple layers is formed, then the electrical connection precision is improved, but the manufacturing process complexity worsens
Solution Approach 1:
The redistribution structure is divided into multiple discrete layers: first insulating layer, first redistribution layer, second insulating layer, and second redistribution layer. Each layer can be formed using standard semiconductor fabrication processes (deposition, etching, planarization) that are well-established in the industry. This segmentation allows precise electrical connections to be achieved through cumulative layer formation rather than attempting to create complex three-dimensional interconnections in a single step.
Data Source
AI summary
A semiconductor package is provided and includes: a base substrate; an interposer package on the base substrate; and first and second semiconductor chips on the interposer package, wherein the interposer package includes: a first redistribution structure including a first insulating layer, a second insulating layer on the first insulating layer, and first and second redistribution layers respectively disposed on the first and second insulating layers; a bridge chip on a bottom surface of the first redistribution structure; a connection structure on the bottom surface of the first redistribution structure and including a plurality of wiring layers electrically connected to the first and second semiconductor chips; and a bonding structure disposed on a third insulating layer on the second insulating layer and bonding each of the first and second semiconductor chips to the first redistribution structure, wherein the second redistribution layer includes a contact plug within the third insulating layer.