Interposer Substrate With Folded Flange For Chip-Scale Package
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Solution Overview
Problem
Current chip-scale packaging technologies face challenges in reducing package size, enhancing robustness and heat transfer, while minimizing fabrication costs and increasing production flexibility, especially in vertically stacking semiconductor dice for higher circuit density on carrier substrates.
Innovation Solution
The development of chip-scale packages with a core member formed from metal or metal alloys, featuring partially folded flange members and an interposer substrate with dielectric insulation, enabling robust design, improved thermal and circuit performance, and the capability to stack multiple semiconductor dice with enhanced electrical and thermal communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional chip-scale packaging is used, then manufacturing simplicity is maintained, but package size reduction and thermal performance are limited
Solution Approach 1:
The package structure is segmented into distinct functional layers: interposer substrate layer, semiconductor die layer, and encapsulant layer. This segmentation allows each layer to be optimized independently for its specific function while achieving overall miniaturization.
Solution Approach 2:
The semiconductor die is nested within a cavity formed in the interposer substrate, and the entire assembly is nested within an encapsulant. This nested configuration maximizes space utilization and reduces the overall package footprint.
2Productivity
If vertically stacked multi-chip module structure is used, then circuit density is increased, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
Bond pads are pre-formed on the interposer substrate at predetermined locations before semiconductor dice are mounted. This preliminary action establishes precise alignment references that guide subsequent die placement and bonding operations.
Solution Approach 2:
The interposer substrate acts as an intermediary carrier that provides a standardized interface between multiple semiconductor dice and the final package structure. It mediates the alignment and electrical connections between stacked dice.
3Strength
If interposer substrate with folded flange members is used, then structural robustness is enhanced, but fabrication complexity increases
Solution Approach 1:
The flange members are merged with the interposer substrate as an integrated structure, formed from the same substrate material. This combining eliminates the need for separate attachment operations and simplifies fabrication while providing enhanced structural strength.
Solution Approach 2:
The flange members are folded into curved configurations rather than remaining flat. This curvature provides structural reinforcement through geometric strength while maintaining compatibility with standard fabrication processes.
4Temperature
If metal core member with dielectric insulation is used, then thermal performance is improved, but manufacturing complexity increases
Solution Approach 1:
The interposer substrate uses composite material construction with a metal core member for thermal conduction and dielectric insulation layers for electrical isolation. This composite structure simultaneously achieves superior thermal performance and electrical functionality.
Solution Approach 2:
Different regions of the interposer substrate have different material properties: the core member region provides thermal conduction, while the dielectric regions provide electrical insulation. This local differentiation of material quality optimizes both thermal and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a minimized footprint, increased robustness, and improved thermal and circuit performance, while reducing fabrication costs and enhancing production flexibility, allowing for the stacking of multiple semiconductor dice with efficient electrical and thermal connectivity.
Implementation Method 1
The routing structures may include conductive elements that provide electrical communication to the semiconductor die, another package, a carrier substrate, and the like
Implementation Method 2
The core member provides, among others, a die attach area for receiving a semiconductor die and at least one folded flange member that extends both laterally away from and back toward and above the die attach area
Implementation Method 3
These designations relate to the physical dimensions of the package, which are only nominally larger than the actual dimensions (length, width, and height) of the unpackaged semiconductor die
Data Source
AI summary
Chip-scale packages and assemblies thereof are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed.